Lines Matching refs:ufs
161 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
162 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
164 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) in exynos_ufs_enable_auto_ctrl_hcc() argument
166 exynos_ufs_auto_ctrl_hcc(ufs, true); in exynos_ufs_enable_auto_ctrl_hcc()
169 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) in exynos_ufs_disable_auto_ctrl_hcc() argument
171 exynos_ufs_auto_ctrl_hcc(ufs, false); in exynos_ufs_disable_auto_ctrl_hcc()
175 struct exynos_ufs *ufs, u32 *val) in exynos_ufs_disable_auto_ctrl_hcc_save() argument
177 *val = hci_readl(ufs, HCI_MISC); in exynos_ufs_disable_auto_ctrl_hcc_save()
178 exynos_ufs_auto_ctrl_hcc(ufs, false); in exynos_ufs_disable_auto_ctrl_hcc_save()
182 struct exynos_ufs *ufs, u32 *val) in exynos_ufs_auto_ctrl_hcc_restore() argument
184 hci_writel(ufs, *val, HCI_MISC); in exynos_ufs_auto_ctrl_hcc_restore()
187 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) in exynos_ufs_gate_clks() argument
189 exynos_ufs_ctrl_clkstop(ufs, true); in exynos_ufs_gate_clks()
192 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) in exynos_ufs_ungate_clks() argument
194 exynos_ufs_ctrl_clkstop(ufs, false); in exynos_ufs_ungate_clks()
197 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) in exynos7_ufs_drv_init() argument
202 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) in exynosauto_ufs_drv_init() argument
204 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynosauto_ufs_drv_init()
207 if (ufs->sysreg) { in exynosauto_ufs_drv_init()
208 return regmap_update_bits(ufs->sysreg, in exynosauto_ufs_drv_init()
209 ufs->shareability_reg_offset, in exynosauto_ufs_drv_init()
218 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) in exynosauto_ufs_post_hce_enable() argument
220 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
225 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); in exynosauto_ufs_post_hce_enable()
227 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); in exynosauto_ufs_post_hce_enable()
232 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) in exynosauto_ufs_pre_link() argument
234 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
238 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
239 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
242 for_each_ufs_rx_lane(ufs, i) { in exynosauto_ufs_pre_link()
244 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
259 for_each_ufs_tx_lane(ufs, i) { in exynosauto_ufs_pre_link()
261 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
286 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, in exynosauto_ufs_pre_pwr_change() argument
289 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
299 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, in exynosauto_ufs_post_pwr_change() argument
302 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
313 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) in exynos7_ufs_pre_link() argument
315 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
316 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite; in exynos7_ufs_pre_link()
320 for_each_ufs_tx_lane(ufs, i) in exynos7_ufs_pre_link()
322 for_each_ufs_rx_lane(ufs, i) { in exynos7_ufs_pre_link()
328 for_each_ufs_tx_lane(ufs, i) in exynos7_ufs_pre_link()
343 static int exynos7_ufs_post_link(struct exynos_ufs *ufs) in exynos7_ufs_post_link() argument
345 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
349 for_each_ufs_tx_lane(ufs, i) { in exynos7_ufs_post_link()
353 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); in exynos7_ufs_post_link()
364 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, in exynos7_ufs_pre_pwr_change() argument
367 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); in exynos7_ufs_pre_pwr_change()
372 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, in exynos7_ufs_post_pwr_change() argument
375 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
395 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) in exynos_ufs_auto_ctrl_hcc() argument
397 u32 misc = hci_readl(ufs, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
400 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
402 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
405 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) in exynos_ufs_ctrl_clkstop() argument
407 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
408 u32 misc = hci_readl(ufs, HCI_MISC); in exynos_ufs_ctrl_clkstop()
411 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); in exynos_ufs_ctrl_clkstop()
412 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
414 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
415 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); in exynos_ufs_ctrl_clkstop()
419 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) in exynos_ufs_get_clk_info() argument
421 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
435 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
437 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
441 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
447 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
448 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
449 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
450 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
452 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
468 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
469 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
475 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) in exynos_ufs_set_unipro_pclk_div() argument
477 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
480 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); in exynos_ufs_set_unipro_pclk_div()
481 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
486 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) in exynos_ufs_set_pwm_clk_div() argument
488 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
489 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
495 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) in exynos_ufs_calc_pwm_clk_div() argument
497 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
498 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
506 clk_period = UNIPRO_PCLK_PERIOD(ufs); in exynos_ufs_calc_pwm_clk_div()
526 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) in exynos_ufs_calc_time_cntr() argument
529 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
532 clk_period = UNIPRO_PCLK_PERIOD(ufs); in exynos_ufs_calc_time_cntr()
538 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) in exynos_ufs_specify_phy_time_attr() argument
540 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
541 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
544 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
546 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
548 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
550 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
552 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
554 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
557 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
559 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
561 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
563 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
565 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
567 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
570 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) in exynos_ufs_config_phy_time_attr() argument
572 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
573 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
576 exynos_ufs_set_pwm_clk_div(ufs); in exynos_ufs_config_phy_time_attr()
580 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_time_attr()
582 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
599 for_each_ufs_tx_lane(ufs, i) { in exynos_ufs_config_phy_time_attr()
618 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
624 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) in exynos_ufs_config_phy_cap_attr() argument
626 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
627 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
632 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
654 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
669 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
693 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) in exynos_ufs_establish_connt() argument
695 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
716 static void exynos_ufs_config_smu(struct exynos_ufs *ufs) in exynos_ufs_config_smu() argument
720 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); in exynos_ufs_config_smu()
723 reg = ufsp_readl(ufs, UFSPRSECURITY); in exynos_ufs_config_smu()
724 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); in exynos_ufs_config_smu()
725 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); in exynos_ufs_config_smu()
726 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); in exynos_ufs_config_smu()
727 ufsp_writel(ufs, 0xff, UFSPSLUN0); in exynos_ufs_config_smu()
728 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); in exynos_ufs_config_smu()
730 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); in exynos_ufs_config_smu()
733 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, in exynos_ufs_config_sync_pattern_mask() argument
736 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
755 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); in exynos_ufs_config_sync_pattern_mask()
760 for_each_ufs_rx_lane(ufs, i) in exynos_ufs_config_sync_pattern_mask()
771 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode() local
772 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
791 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
792 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
795 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
819 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode() local
820 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
832 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
833 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
859 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req() local
862 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
865 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
867 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
873 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req() local
876 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
881 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
887 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
892 static int exynos_ufs_phy_init(struct exynos_ufs *ufs) in exynos_ufs_phy_init() argument
894 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
895 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
898 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
900 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
902 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
903 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
905 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
908 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
928 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) in exynos_ufs_config_unipro() argument
930 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
933 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
935 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
937 ufs->drv_data->uic_attr->pa_dbg_option_suite); in exynos_ufs_config_unipro()
940 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) in exynos_ufs_config_intr() argument
944 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); in exynos_ufs_config_intr()
947 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); in exynos_ufs_config_intr()
950 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); in exynos_ufs_config_intr()
953 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); in exynos_ufs_config_intr()
956 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); in exynos_ufs_config_intr()
964 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_setup_clocks() local
966 if (!ufs) in exynos_ufs_setup_clocks()
970 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
971 exynos_ufs_disable_auto_ctrl_hcc(ufs); in exynos_ufs_setup_clocks()
972 exynos_ufs_ungate_clks(ufs); in exynos_ufs_setup_clocks()
974 exynos_ufs_gate_clks(ufs); in exynos_ufs_setup_clocks()
975 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
976 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_setup_clocks()
984 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link() local
987 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); in exynos_ufs_pre_link()
988 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); in exynos_ufs_pre_link()
989 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); in exynos_ufs_pre_link()
990 exynos_ufs_set_unipro_pclk_div(ufs); in exynos_ufs_pre_link()
993 exynos_ufs_config_unipro(ufs); in exynos_ufs_pre_link()
996 exynos_ufs_phy_init(ufs); in exynos_ufs_pre_link()
997 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
998 exynos_ufs_config_phy_time_attr(ufs); in exynos_ufs_pre_link()
999 exynos_ufs_config_phy_cap_attr(ufs); in exynos_ufs_pre_link()
1004 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
1005 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1010 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) in exynos_ufs_fit_aggr_timeout() argument
1014 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); in exynos_ufs_fit_aggr_timeout()
1015 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); in exynos_ufs_fit_aggr_timeout()
1020 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link() local
1021 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1022 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1024 exynos_ufs_establish_connt(ufs); in exynos_ufs_post_link()
1025 exynos_ufs_fit_aggr_timeout(ufs); in exynos_ufs_post_link()
1027 hci_writel(ufs, 0xa, HCI_DATA_REORDER); in exynos_ufs_post_link()
1028 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE); in exynos_ufs_post_link()
1029 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE); in exynos_ufs_post_link()
1030 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1031 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1032 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); in exynos_ufs_post_link()
1034 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1048 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1053 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1077 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1078 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1083 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) in exynos_ufs_parse_dt() argument
1089 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1091 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1092 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1099 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1100 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1101 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1104 &ufs->shareability_reg_offset)) { in exynos_ufs_parse_dt()
1106 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1110 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1111 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1125 struct exynos_ufs *ufs) in exynos_ufs_priv_init() argument
1127 ufs->hba = hba; in exynos_ufs_priv_init()
1128 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1129 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1130 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1131 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1132 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1133 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1140 struct exynos_ufs *ufs; in exynos_ufs_init() local
1143 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); in exynos_ufs_init()
1144 if (!ufs) in exynos_ufs_init()
1148 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1149 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1151 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1155 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1156 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1158 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1162 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1163 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1165 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1168 ret = exynos_ufs_parse_dt(dev, ufs); in exynos_ufs_init()
1174 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1175 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1176 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1181 exynos_ufs_priv_init(hba, ufs); in exynos_ufs_init()
1183 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1184 ret = ufs->drv_data->drv_init(dev, ufs); in exynos_ufs_init()
1191 ret = exynos_ufs_get_clk_info(ufs); in exynos_ufs_init()
1194 exynos_ufs_specify_phy_time_attr(ufs); in exynos_ufs_init()
1195 exynos_ufs_config_smu(ufs); in exynos_ufs_init()
1205 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset() local
1210 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); in exynos_ufs_host_reset()
1212 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); in exynos_ufs_host_reset()
1215 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) in exynos_ufs_host_reset()
1223 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); in exynos_ufs_host_reset()
1229 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset() local
1231 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); in exynos_ufs_dev_hw_reset()
1233 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); in exynos_ufs_dev_hw_reset()
1238 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8() local
1239 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1242 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1243 exynos_ufs_disable_auto_ctrl_hcc(ufs); in exynos_ufs_pre_hibern8()
1244 exynos_ufs_ungate_clks(ufs); in exynos_ufs_pre_hibern8()
1246 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1257 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1271 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8() local
1277 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) in exynos_ufs_post_hibern8()
1290 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) in exynos_ufs_post_hibern8()
1291 exynos_ufs_establish_connt(ufs); in exynos_ufs_post_hibern8()
1293 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1294 exynos_ufs_gate_clks(ufs); in exynos_ufs_post_hibern8()
1295 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1296 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_post_hibern8()
1303 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify() local
1308 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1309 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1320 exynos_ufs_calc_pwm_clk_div(ufs); in exynos_ufs_hce_enable_notify()
1321 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1322 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_hce_enable_notify()
1324 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1325 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1387 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend() local
1393 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1400 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume() local
1403 phy_power_on(ufs->phy); in exynos_ufs_resume()
1405 exynos_ufs_config_smu(ufs); in exynos_ufs_resume()
1447 struct exynos_ufs *ufs; in exynosauto_ufs_vh_init() local
1450 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); in exynosauto_ufs_vh_init()
1451 if (!ufs) in exynosauto_ufs_vh_init()
1455 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1456 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1458 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1465 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1466 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1469 exynos_ufs_priv_init(hba, ufs); in exynosauto_ufs_vh_init()
1515 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_remove() local
1520 phy_power_off(ufs->phy); in exynos_ufs_remove()
1521 phy_exit(ufs->phy); in exynos_ufs_remove()