44 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
46 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
48 		{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,  in tc_dwc_g210_setup_40bit_rmmi()
50 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
54 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
56 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_40bit_rmmi()
58 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_40bit_rmmi()
60 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_40bit_rmmi()
62 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_40bit_rmmi()
64 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
66 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
68 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_40bit_rmmi()
70 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_40bit_rmmi()
72 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
74 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
97 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
103 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
105 		{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
107 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
111 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
113 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
115 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
117 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
119 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
121 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
123 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
125 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
127 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane0()