159 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =  in read_inbnd_queue_table()
161 		pm8001_ha->inbnd_q_tbl[i].pi_offset =  in read_inbnd_queue_table()
228 		pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt	=  in init_default_table_values()
230 		pm8001_ha->inbnd_q_tbl[i].upper_base_addr	=  in init_default_table_values()
232 		pm8001_ha->inbnd_q_tbl[i].lower_base_addr	=  in init_default_table_values()
234 		pm8001_ha->inbnd_q_tbl[i].base_virt		=  in init_default_table_values()
236 		pm8001_ha->inbnd_q_tbl[i].total_length		=  in init_default_table_values()
238 		pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr	=  in init_default_table_values()
240 		pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr	=  in init_default_table_values()
242 		pm8001_ha->inbnd_q_tbl[i].ci_virt		=  in init_default_table_values()
244 		pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);  in init_default_table_values()
246 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar		=  in init_default_table_values()
249 		pm8001_ha->inbnd_q_tbl[i].pi_offset		=  in init_default_table_values()
251 		pm8001_ha->inbnd_q_tbl[i].producer_idx		= 0;  in init_default_table_values()
252 		pm8001_ha->inbnd_q_tbl[i].consumer_index	= 0;  in init_default_table_values()
351 		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);  in update_inbnd_queue_table()
353 		pm8001_ha->inbnd_q_tbl[number].upper_base_addr);  in update_inbnd_queue_table()
355 		pm8001_ha->inbnd_q_tbl[number].lower_base_addr);  in update_inbnd_queue_table()
357 		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);  in update_inbnd_queue_table()
359 		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);  in update_inbnd_queue_table()
1325 	struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index];  in pm8001_mpi_build_cmd()