Lines Matching refs:BIT
83 # define IRQSTATUS_LATCHED_MSG BIT(0)
84 # define IRQSTATUS_LATCHED_IO BIT(1)
85 # define IRQSTATUS_LATCHED_CD BIT(2)
86 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
87 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
88 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
89 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
90 # define IRQSTATUS_TIMER_IRQ BIT(7)
91 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
92 # define IRQSTATUS_PCI_IRQ BIT(9)
93 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
94 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
95 # define PCI_IRQ_MASK BIT(12)
96 # define TIMER_IRQ_MASK BIT(13)
97 # define FIFO_IRQ_MASK BIT(14)
98 # define SCSI_IRQ_MASK BIT(15)
114 # define CB_MMIO_MODE BIT(0)
115 # define CB_IO_MODE BIT(1)
116 # define BM_TEST BIT(2)
117 # define BM_TEST_DIR BIT(3)
118 # define DUAL_EDGE_ENABLE BIT(4)
119 # define NO_TRANSFER_TO_HOST BIT(5)
120 # define TRANSFER_GO BIT(7)
121 # define BLIEND_MODE BIT(8)
122 # define BM_START BIT(9)
123 # define ADVANCED_BM_WRITE BIT(10)
124 # define BM_SINGLE_MODE BIT(11)
125 # define FIFO_TRUE_FULL BIT(12)
126 # define FIFO_TRUE_EMPTY BIT(13)
127 # define ALL_COUNTER_CLR BIT(14)
128 # define FIFOTEST BIT(15)
134 # define TIMER_STOP BIT(8)
141 # define FIFO_EMPTY_SHLD_FLAG BIT(14)
142 # define FIFO_FULL_SHLD_FLAG BIT(15)
145 # define SREQSMPLRATE_RATE0 BIT(0)
146 # define SREQSMPLRATE_RATE1 BIT(1)
147 # define SAMPLING_ENABLE BIT(2)
153 # define BUSCTL_SEL BIT(0)
154 # define BUSCTL_RST BIT(1)
155 # define BUSCTL_DATAOUT_ENB BIT(2)
156 # define BUSCTL_ATN BIT(3)
157 # define BUSCTL_ACK BIT(4)
158 # define BUSCTL_BSY BIT(5)
159 # define AUTODIRECTION BIT(6)
160 # define ACKENB BIT(7)
163 # define ACK_COUNTER_CLR BIT(0)
164 # define SREQ_COUNTER_CLR BIT(1)
165 # define FIFO_HOST_POINTER_CLR BIT(2)
166 # define FIFO_REST_COUNT_CLR BIT(3)
167 # define BM_COUNTER_CLR BIT(4)
168 # define SAVED_ACK_CLR BIT(5)
177 # define BUSMON_MSG BIT(0)
178 # define BUSMON_IO BIT(1)
179 # define BUSMON_CD BIT(2)
180 # define BUSMON_BSY BIT(3)
181 # define BUSMON_ACK BIT(4)
182 # define BUSMON_REQ BIT(5)
183 # define BUSMON_SEL BIT(6)
184 # define BUSMON_ATN BIT(7)
189 # define PARITY_CHECK_ENABLE BIT(0)
190 # define PARITY_ERROR_CLEAR BIT(1)
193 # define PARITY_ERROR_NORMAL BIT(1)
194 # define PARITY_ERROR_LSB BIT(1)
195 # define PARITY_ERROR_MSB BIT(2)
200 # define CLEAR_CDB_FIFO_POINTER BIT(0)
201 # define AUTO_COMMAND_PHASE BIT(1)
202 # define AUTOSCSI_START BIT(2)
203 # define AUTOSCSI_RESTART BIT(3)
204 # define AUTO_PARAMETER BIT(4)
205 # define AUTO_ATN BIT(5)
206 # define AUTO_MSGIN_00_OR_04 BIT(6)
207 # define AUTO_MSGIN_02 BIT(7)
208 # define AUTO_MSGIN_03 BIT(8)
211 # define ARBIT_GO BIT(0)
212 # define ARBIT_CLEAR BIT(1)
216 # define ARBIT_WIN BIT(1)
217 # define ARBIT_FAIL BIT(2)
218 # define AUTO_PARAMETER_VALID BIT(3)
219 # define SGT_VALID BIT(4)
231 # define SCAM_MSG BIT(0)
232 # define SCAM_IO BIT(1)
233 # define SCAM_CD BIT(2)
234 # define SCAM_BSY BIT(3)
235 # define SCAM_SEL BIT(4)
236 # define SCAM_XFEROK BIT(5)
239 # define SD0 BIT(0)
240 # define SD1 BIT(1)
241 # define SD2 BIT(2)
242 # define SD3 BIT(3)
243 # define SD4 BIT(4)
244 # define SD5 BIT(5)
245 # define SD6 BIT(6)
246 # define SD7 BIT(7)
257 # define SGTEND BIT(31) /* Last SGT marker */
263 # define COMMAND_PHASE BIT(0)
264 # define DATA_IN_PHASE BIT(1)
265 # define DATA_OUT_PHASE BIT(2)
266 # define MSGOUT_PHASE BIT(3)
267 # define STATUS_PHASE BIT(4)
268 # define ILLEGAL_PHASE BIT(5)
269 # define BUS_FREE_OCCUER BIT(6)
270 # define MSG_IN_OCCUER BIT(7)
271 # define MSG_OUT_OCCUER BIT(8)
272 # define SELECTION_TIMEOUT BIT(9)
273 # define MSGIN_00_VALID BIT(10)
274 # define MSGIN_02_VALID BIT(11)
275 # define MSGIN_03_VALID BIT(12)
276 # define MSGIN_04_VALID BIT(13)
277 # define AUTOSCSI_BUSY BIT(15)
282 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
283 # define MV_VALID BIT(7)
299 # define CLOCK_2 BIT(0) /* MCLK/2 */
300 # define CLOCK_4 BIT(1) /* MCLK/4 */
301 # define PCICLK BIT(7) /* PCICLK (33MHz) */
304 # define BPWR BIT(0)
305 # define SENSE BIT(1) /* Read Only */
310 # define LED_OFF BIT(0)
313 # define IRQSELECT_RESELECT_IRQ BIT(0)
314 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
315 # define IRQSELECT_SCSIRESET_IRQ BIT(2)
316 # define IRQSELECT_TIMER_IRQ BIT(3)
317 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
318 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
319 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
320 # define IRQSELECT_SERR_IRQ BIT(7)
321 # define IRQSELECT_PERR_IRQ BIT(8)
322 # define IRQSELECT_BMCNTERR_IRQ BIT(9)
323 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
326 # define OLD_MSG BIT(0)
327 # define OLD_IO BIT(1)
328 # define OLD_CD BIT(2)
329 # define OLD_BUSY BIT(3)
335 # define ROM_WRITE_ENB BIT(0)
336 # define IO_ACCESS_ENB BIT(1)
337 # define ROM_ADR_CLEAR BIT(2)
344 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
345 # define OEM1 BIT(2) /* OEM select */
346 # define OPTB BIT(3) /* KME mode select */
347 # define OPTC BIT(4) /* KME mode select */
348 # define OPTD BIT(5) /* KME mode select */
349 # define OPTE BIT(6) /* KME mode select */
350 # define OPTF BIT(7) /* Power management */
354 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
355 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
356 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
357 # define DELAYED_BMSTART BIT(3)
358 # define MASTER_TERMINATION_SELECT BIT(4)
359 # define BMREQ_NEGATE_TIMING_SEL BIT(5)
360 # define AUTOSEL_TIMING_SEL BIT(6)
361 # define MISC_MABORT_MASK BIT(7)
362 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
365 # define BM_CYCLE0 BIT(0)
366 # define BM_CYCLE1 BIT(1)
367 # define BM_FRAME_ASSERT_TIMING BIT(2)
368 # define BM_IRDY_ASSERT_TIMING BIT(3)
369 # define BM_SINGLE_BUS_MASTER BIT(4)
370 # define MEMRD_CMD0 BIT(5)
371 # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
372 # define MEMRD_CMD1 BIT(7)
376 # define SREQ_EDGH_SELECT BIT(0)
379 # define REQCNT_UP BIT(0)
380 # define ACKCNT_UP BIT(1)
381 # define BMADR_UP BIT(4)
382 # define BMCNT_UP BIT(5)
383 # define SGT_CNT_UP BIT(7)
392 # define SCL BIT(0)
393 # define ENA BIT(1)
394 # define SDA BIT(2)
473 #define NSP32_TRANSFER_BUSMASTER BIT(0)
474 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
475 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
484 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
485 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
519 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
520 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
521 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */