Lines Matching refs:MVS_CHIP_DISP
147 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset); in mvs_free_reg_set()
155 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset); in mvs_assign_reg_set()
164 MVS_CHIP_DISP->phy_reset(mvi, no, hard); in mvs_phys_reset()
186 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata); in mvs_phy_control()
190 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id); in mvs_phy_control()
193 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET); in mvs_phy_control()
197 MVS_CHIP_DISP->phy_enable(mvi, phy_id); in mvs_phy_control()
198 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET); in mvs_phy_control()
202 MVS_CHIP_DISP->phy_disable(mvi, phy_id); in mvs_phy_control()
218 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo); in mvs_set_sas_addr()
219 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo); in mvs_set_sas_addr()
220 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi); in mvs_set_sas_addr()
221 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi); in mvs_set_sas_addr()
246 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate(); in mvs_bytes_dmaed()
259 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT); in mvs_bytes_dmaed()
260 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00); in mvs_bytes_dmaed()
369 i = MVS_CHIP_DISP->prd_size() * tei->n_elem; in mvs_task_prep_smp()
400 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd); in mvs_task_prep_smp()
463 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT); in mvs_task_prep_ata()
513 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count(); in mvs_task_prep_ata()
548 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd); in mvs_task_prep_ata()
551 MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask, in mvs_task_prep_ata()
629 i = MVS_CHIP_DISP->prd_size() * tei->n_elem; in mvs_task_prep_ssp()
693 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd); in mvs_task_prep_ssp()
857 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) & in mvs_queue_command()
918 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no, in mvs_update_wideport()
920 MVS_CHIP_DISP->write_port_cfg_data(mvi, no, in mvs_update_wideport()
923 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no, in mvs_update_wideport()
925 MVS_CHIP_DISP->write_port_cfg_data(mvi, no, in mvs_update_wideport()
937 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i); in mvs_is_phy_ready()
966 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3); in mvs_get_d2h_reg()
967 s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i)); in mvs_get_d2h_reg()
969 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2); in mvs_get_d2h_reg()
970 s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i)); in mvs_get_d2h_reg()
972 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1); in mvs_get_d2h_reg()
973 s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i)); in mvs_get_d2h_reg()
975 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0); in mvs_get_d2h_reg()
976 s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i)); in mvs_get_d2h_reg()
1004 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i); in mvs_update_phyinfo()
1012 oob_done = MVS_CHIP_DISP->oob_done(mvi, i); in mvs_update_phyinfo()
1014 MVS_CHIP_DISP->fix_phy_info(mvi, i, id); in mvs_update_phyinfo()
1031 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i); in mvs_update_phyinfo()
1032 MVS_CHIP_DISP->write_port_irq_mask(mvi, i, in mvs_update_phyinfo()
1058 if (MVS_CHIP_DISP->phy_work_around) in mvs_update_phyinfo()
1059 MVS_CHIP_DISP->phy_work_around(mvi, i); in mvs_update_phyinfo()
1067 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status); in mvs_update_phyinfo()
1104 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT); in mvs_port_notify_formed()
1105 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04); in mvs_port_notify_formed()
1499 MVS_CHIP_DISP->issue_stop(mvi, type, tfs); in mvs_slot_err()
1501 MVS_CHIP_DISP->command_active(mvi, slot_idx); in mvs_slot_err()
1692 MVS_CHIP_DISP->command_active(mvi, slot_idx); in mvs_do_release_task()
1730 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no); in mvs_work_queue()
1739 MVS_CHIP_DISP->detect_porttype(mvi, phy_no); in mvs_work_queue()
1786 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET); in mvs_sig_time_out()
1796 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no); in mvs_int_port()
1797 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status); in mvs_int_port()
1799 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no)); in mvs_int_port()
1820 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1); in mvs_int_port()
1826 if (MVS_CHIP_DISP->stp_reset) in mvs_int_port()
1827 MVS_CHIP_DISP->stp_reset(mvi, in mvs_int_port()
1830 MVS_CHIP_DISP->phy_reset(mvi, in mvs_int_port()
1838 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no); in mvs_int_port()
1839 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no, in mvs_int_port()
1852 MVS_CHIP_DISP->detect_porttype(mvi, phy_no); in mvs_int_port()
1854 tmp = MVS_CHIP_DISP->read_port_irq_mask( in mvs_int_port()
1857 MVS_CHIP_DISP->write_port_irq_mask(mvi, in mvs_int_port()
1862 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE); in mvs_int_port()
1904 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK; in mvs_int_rx()
1927 MVS_CHIP_DISP->int_full(mvi); in mvs_int_rx()
1937 if (MVS_CHIP_DISP->gpio_write) { in mvs_gpio_write()
1938 return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type, in mvs_gpio_write()