Lines Matching refs:phy_no
555 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, in hisi_sas_phy_write32() argument
558 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; in hisi_sas_phy_write32()
564 int phy_no, u32 off) in hisi_sas_phy_read32() argument
566 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; in hisi_sas_phy_read32()
739 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in config_phy_opt_mode_v3_hw() argument
741 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); in config_phy_opt_mode_v3_hw()
745 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); in config_phy_opt_mode_v3_hw()
748 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in config_id_frame_v3_hw() argument
761 identify_frame.phy_id = phy_no; in config_id_frame_v3_hw()
764 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, in config_id_frame_v3_hw()
766 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, in config_id_frame_v3_hw()
768 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, in config_id_frame_v3_hw()
770 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, in config_id_frame_v3_hw()
772 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, in config_id_frame_v3_hw()
774 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, in config_id_frame_v3_hw()
959 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in enable_phy_v3_hw() argument
961 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); in enable_phy_v3_hw()
965 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); in enable_phy_v3_hw()
968 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in disable_phy_v3_hw() argument
970 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); in disable_phy_v3_hw()
971 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); in disable_phy_v3_hw()
977 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); in disable_phy_v3_hw()
980 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); in disable_phy_v3_hw()
985 if (state & BIT(phy_no)) { in disable_phy_v3_hw()
987 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); in disable_phy_v3_hw()
992 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); in disable_phy_v3_hw()
993 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); in disable_phy_v3_hw()
994 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); in disable_phy_v3_hw()
996 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); in disable_phy_v3_hw()
997 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); in disable_phy_v3_hw()
1000 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in start_phy_v3_hw() argument
1002 config_id_frame_v3_hw(hisi_hba, phy_no); in start_phy_v3_hw()
1003 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); in start_phy_v3_hw()
1004 enable_phy_v3_hw(hisi_hba, phy_no); in start_phy_v3_hw()
1007 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in phy_hard_reset_v3_hw() argument
1009 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in phy_hard_reset_v3_hw()
1012 hisi_sas_phy_enable(hisi_hba, phy_no, 0); in phy_hard_reset_v3_hw()
1014 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); in phy_hard_reset_v3_hw()
1015 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, in phy_hard_reset_v3_hw()
1019 hisi_sas_phy_enable(hisi_hba, phy_no, 1); in phy_hard_reset_v3_hw()
1042 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in sl_notify_ssp_v3_hw() argument
1046 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); in sl_notify_ssp_v3_hw()
1048 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); in sl_notify_ssp_v3_hw()
1050 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); in sl_notify_ssp_v3_hw()
1052 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); in sl_notify_ssp_v3_hw()
1480 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) in phy_up_v3_hw() argument
1485 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in phy_up_v3_hw()
1489 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); in phy_up_v3_hw()
1492 port_id = (port_id >> (4 * phy_no)) & 0xf; in phy_up_v3_hw()
1494 link_rate = (link_rate >> (phy_no * 4)) & 0xf; in phy_up_v3_hw()
1497 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); in phy_up_v3_hw()
1506 if (context & (1 << phy_no)) { in phy_up_v3_hw()
1512 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); in phy_up_v3_hw()
1513 initial_fis = &hisi_hba->initial_fis[phy_no]; in phy_up_v3_hw()
1519 phy_no, fis->status); in phy_up_v3_hw()
1528 attached_sas_addr[7] = phy_no; in phy_up_v3_hw()
1543 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); in phy_up_v3_hw()
1545 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, in phy_up_v3_hw()
1586 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_up_v3_hw()
1588 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); in phy_up_v3_hw()
1593 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) in phy_down_v3_hw() argument
1595 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in phy_down_v3_hw()
1602 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); in phy_down_v3_hw()
1605 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); in phy_down_v3_hw()
1606 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0, in phy_down_v3_hw()
1609 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); in phy_down_v3_hw()
1610 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, in phy_down_v3_hw()
1613 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); in phy_down_v3_hw()
1614 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, in phy_down_v3_hw()
1617 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); in phy_down_v3_hw()
1618 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); in phy_down_v3_hw()
1623 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) in phy_bcast_v3_hw() argument
1625 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in phy_bcast_v3_hw()
1629 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); in phy_bcast_v3_hw()
1630 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); in phy_bcast_v3_hw()
1635 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_bcast_v3_hw()
1637 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); in phy_bcast_v3_hw()
1646 int phy_no = 0; in int_phy_up_down_bcast_v3_hw() local
1653 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, in int_phy_up_down_bcast_v3_hw()
1656 int rdy = phy_state & (1 << phy_no); in int_phy_up_down_bcast_v3_hw()
1661 if (phy_up_v3_hw(phy_no, hisi_hba) in int_phy_up_down_bcast_v3_hw()
1666 if (phy_bcast_v3_hw(phy_no, hisi_hba) in int_phy_up_down_bcast_v3_hw()
1672 if (phy_down_v3_hw(phy_no, hisi_hba) in int_phy_up_down_bcast_v3_hw()
1678 phy_no++; in int_phy_up_down_bcast_v3_hw()
1727 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in handle_chl_int1_v3_hw() argument
1729 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); in handle_chl_int1_v3_hw()
1730 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); in handle_chl_int1_v3_hw()
1737 phy_no); in handle_chl_int1_v3_hw()
1748 error->msg, phy_no, irq_value); in handle_chl_int1_v3_hw()
1752 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); in handle_chl_int1_v3_hw()
1755 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in phy_get_events_v3_hw() argument
1757 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in phy_get_events_v3_hw()
1766 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); in phy_get_events_v3_hw()
1770 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); in phy_get_events_v3_hw()
1774 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); in phy_get_events_v3_hw()
1778 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); in phy_get_events_v3_hw()
1782 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); in phy_get_events_v3_hw()
1788 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in handle_chl_int2_v3_hw() argument
1790 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); in handle_chl_int2_v3_hw()
1791 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in handle_chl_int2_v3_hw()
1792 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in handle_chl_int2_v3_hw()
1802 phy_no); in handle_chl_int2_v3_hw()
1807 dev_warn(dev, "phy%d identify timeout\n", phy_no); in handle_chl_int2_v3_hw()
1812 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, in handle_chl_int2_v3_hw()
1816 phy_no, reg_value); in handle_chl_int2_v3_hw()
1825 phy_get_events_v3_hw(hisi_hba, phy_no); in handle_chl_int2_v3_hw()
1828 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, in handle_chl_int2_v3_hw()
1832 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, in handle_chl_int2_v3_hw()
1836 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, in handle_chl_int2_v3_hw()
1847 !((reg_value >> 8) & BIT(phy_no)), in handle_chl_int2_v3_hw()
1853 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); in handle_chl_int2_v3_hw()
1856 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) in handle_chl_int0_v3_hw() argument
1858 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in handle_chl_int0_v3_hw()
1861 hisi_sas_phy_oob_ready(hisi_hba, phy_no); in handle_chl_int0_v3_hw()
1863 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in handle_chl_int0_v3_hw()
1873 int phy_no = 0; in int_chnl_int_v3_hw() local
1879 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH))) in int_chnl_int_v3_hw()
1880 handle_chl_int0_v3_hw(hisi_hba, phy_no); in int_chnl_int_v3_hw()
1882 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH))) in int_chnl_int_v3_hw()
1883 handle_chl_int1_v3_hw(hisi_hba, phy_no); in int_chnl_int_v3_hw()
1885 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH))) in int_chnl_int_v3_hw()
1886 handle_chl_int2_v3_hw(hisi_hba, phy_no); in int_chnl_int_v3_hw()
1888 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH)); in int_chnl_int_v3_hw()
1889 phy_no++; in int_chnl_int_v3_hw()
2528 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, in phy_set_linkrate_v3_hw() argument
2532 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no, in phy_set_linkrate_v3_hw()
2537 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, in phy_set_linkrate_v3_hw()
3047 int phy_no = hisi_hba->debugfs_bist_phy_no; in hisi_sas_bist_test_prep_v3_hw() local
3051 hisi_sas_phy_enable(hisi_hba, phy_no, 0); in hisi_sas_bist_test_prep_v3_hw()
3055 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4), in hisi_sas_bist_test_prep_v3_hw()
3056 hisi_hba->debugfs_bist_ffe[phy_no][i]); in hisi_sas_bist_test_prep_v3_hw()
3059 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG); in hisi_sas_bist_test_prep_v3_hw()
3061 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val); in hisi_sas_bist_test_prep_v3_hw()
3067 int phy_no = hisi_hba->debugfs_bist_phy_no; in hisi_sas_bist_test_restore_v3_hw() local
3070 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL); in hisi_sas_bist_test_restore_v3_hw()
3073 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val); in hisi_sas_bist_test_restore_v3_hw()
3076 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG); in hisi_sas_bist_test_restore_v3_hw()
3078 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val); in hisi_sas_bist_test_restore_v3_hw()
3081 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE); in hisi_sas_bist_test_restore_v3_hw()
3085 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val); in hisi_sas_bist_test_restore_v3_hw()
3088 hisi_sas_phy_enable(hisi_hba, phy_no, 1); in hisi_sas_bist_test_restore_v3_hw()
3097 u32 phy_no = hisi_hba->debugfs_bist_phy_no; in debugfs_set_bist_v3_hw() local
3098 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no]; in debugfs_set_bist_v3_hw()
3105 phy_no, linkrate, code_mode, path_mode, in debugfs_set_bist_v3_hw()
3117 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3121 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, in debugfs_set_bist_v3_hw()
3125 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3133 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, in debugfs_set_bist_v3_hw()
3139 hisi_sas_phy_write32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3143 hisi_sas_phy_write32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3146 hisi_sas_phy_write32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3149 hisi_sas_phy_write32(hisi_hba, phy_no, in debugfs_set_bist_v3_hw()
3156 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, in debugfs_set_bist_v3_hw()
3161 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT); in debugfs_set_bist_v3_hw()
3165 phy_no, SAS_BIST_ERR_CNT); in debugfs_set_bist_v3_hw()
3961 unsigned int phy_no; in debugfs_bist_phy_v3_hw_write() local
3967 val = kstrtouint_from_user(buf, count, 0, &phy_no); in debugfs_bist_phy_v3_hw_write()
3971 if (phy_no >= hisi_hba->n_phy) in debugfs_bist_phy_v3_hw_write()
3974 hisi_hba->debugfs_bist_phy_no = phy_no; in debugfs_bist_phy_v3_hw_write()
4338 int phy_no = phy->sas_phy.id; in debugfs_update_fifo_config_v3_hw() local
4347 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_update_fifo_config_v3_hw()
4359 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val); in debugfs_update_fifo_config_v3_hw()
4361 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK, in debugfs_update_fifo_config_v3_hw()
4364 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER, in debugfs_update_fifo_config_v3_hw()
4367 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK, in debugfs_update_fifo_config_v3_hw()
4371 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_update_fifo_config_v3_hw()
4373 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val); in debugfs_update_fifo_config_v3_hw()
4410 int phy_no = phy->sas_phy.id; in debugfs_read_fifo_data_v3_hw() local
4417 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_read_fifo_data_v3_hw()
4419 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val); in debugfs_read_fifo_data_v3_hw()
4422 val = hisi_sas_phy_read32(hisi_hba, phy_no, in debugfs_read_fifo_data_v3_hw()
4428 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_read_fifo_data_v3_hw()
4430 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val); in debugfs_read_fifo_data_v3_hw()
4448 int phy_no; in debugfs_fifo_init_v3_hw() local
4453 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { in debugfs_fifo_init_v3_hw()
4454 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; in debugfs_fifo_init_v3_hw()
4460 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_fifo_init_v3_hw()
4465 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_fifo_init_v3_hw()
4470 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL); in debugfs_fifo_init_v3_hw()
4475 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK); in debugfs_fifo_init_v3_hw()
4478 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER); in debugfs_fifo_init_v3_hw()
4480 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK); in debugfs_fifo_init_v3_hw()
4483 snprintf(name, 256, "%d", phy_no); in debugfs_fifo_init_v3_hw()
4651 int phy_no; in debugfs_phy_down_cnt_init_v3_hw() local
4653 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { in debugfs_phy_down_cnt_init_v3_hw()
4654 snprintf(name, 16, "%d", phy_no); in debugfs_phy_down_cnt_init_v3_hw()
4656 &hisi_hba->phy[phy_no], in debugfs_phy_down_cnt_init_v3_hw()
4664 int phy_no; in debugfs_bist_init_v3_hw() local
4701 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { in debugfs_bist_init_v3_hw()
4707 snprintf(name, 256, "%d", phy_no); in debugfs_bist_init_v3_hw()
4715 &hisi_hba->debugfs_bist_ffe[phy_no][i], in debugfs_bist_init_v3_hw()