750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,  in hisi_sas_phy_write32()  argument
753 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;  in hisi_sas_phy_write32()
759 				      int phy_no, u32 off)  in hisi_sas_phy_read32()  argument
761 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;  in hisi_sas_phy_read32()
882 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in config_phy_opt_mode_v2_hw()  argument
884 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);  in config_phy_opt_mode_v2_hw()
888 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);  in config_phy_opt_mode_v2_hw()
891 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in config_id_frame_v2_hw()  argument
904 	identify_frame.phy_id = phy_no;  in config_id_frame_v2_hw()
907 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,  in config_id_frame_v2_hw()
909 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,  in config_id_frame_v2_hw()
911 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,  in config_id_frame_v2_hw()
913 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,  in config_id_frame_v2_hw()
915 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,  in config_id_frame_v2_hw()
917 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,  in config_id_frame_v2_hw()
1121 	int phy_no;  in phys_reject_stp_links_v2_hw()  local
1124 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {  in phys_reject_stp_links_v2_hw()
1125 		cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);  in phys_reject_stp_links_v2_hw()
1130 		hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);  in phys_reject_stp_links_v2_hw()
1136 	int phy_no;  in phys_try_accept_stp_links_v2_hw()  local
1139 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {  in phys_try_accept_stp_links_v2_hw()
1140 		if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))  in phys_try_accept_stp_links_v2_hw()
1143 		dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,  in phys_try_accept_stp_links_v2_hw()
1147 				phy_no, CON_CONTROL);  in phys_try_accept_stp_links_v2_hw()
1150 			hisi_sas_phy_write32(hisi_hba, phy_no,  in phys_try_accept_stp_links_v2_hw()
1152 			clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);  in phys_try_accept_stp_links_v2_hw()
1395 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in enable_phy_v2_hw()  argument
1397 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);  in enable_phy_v2_hw()
1400 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);  in enable_phy_v2_hw()
1403 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in is_sata_phy_v2_hw()  argument
1408 	if (context & (1 << phy_no))  in is_sata_phy_v2_hw()
1414 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in tx_fifo_is_empty_v2_hw()  argument
1418 	dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);  in tx_fifo_is_empty_v2_hw()
1426 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in axi_bus_is_idle_v2_hw()  argument
1437 		dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);  in axi_bus_is_idle_v2_hw()
1439 			phy_no, DMA_TX_FIFO_DFX0);  in axi_bus_is_idle_v2_hw()
1447 			phy_no, status, axi_status,  in axi_bus_is_idle_v2_hw()
1452 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in wait_io_done_v2_hw()  argument
1459 		status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);  in wait_io_done_v2_hw()
1465 		tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);  in wait_io_done_v2_hw()
1471 			phy_no, status, tx_dfx0);  in wait_io_done_v2_hw()
1475 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in allowed_disable_phy_v2_hw()  argument
1477 	if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))  in allowed_disable_phy_v2_hw()
1480 	if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))  in allowed_disable_phy_v2_hw()
1483 	if (!wait_io_done_v2_hw(hisi_hba, phy_no))  in allowed_disable_phy_v2_hw()
1490 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in disable_phy_v2_hw()  argument
1502 	if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {  in disable_phy_v2_hw()
1503 		if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))  in disable_phy_v2_hw()
1511 	dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);  in disable_phy_v2_hw()
1516 	if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {  in disable_phy_v2_hw()
1518 			phy_no);  in disable_phy_v2_hw()
1519 		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,  in disable_phy_v2_hw()
1522 		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,  in disable_phy_v2_hw()
1527 	cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);  in disable_phy_v2_hw()
1529 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);  in disable_phy_v2_hw()
1537 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in start_phy_v2_hw()  argument
1539 	config_id_frame_v2_hw(hisi_hba, phy_no);  in start_phy_v2_hw()
1540 	config_phy_opt_mode_v2_hw(hisi_hba, phy_no);  in start_phy_v2_hw()
1541 	enable_phy_v2_hw(hisi_hba, phy_no);  in start_phy_v2_hw()
1544 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in phy_hard_reset_v2_hw()  argument
1546 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in phy_hard_reset_v2_hw()
1549 	hisi_sas_phy_enable(hisi_hba, phy_no, 0);  in phy_hard_reset_v2_hw()
1551 		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);  in phy_hard_reset_v2_hw()
1552 		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,  in phy_hard_reset_v2_hw()
1556 	hisi_sas_phy_enable(hisi_hba, phy_no, 1);  in phy_hard_reset_v2_hw()
1559 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in phy_get_events_v2_hw()  argument
1561 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in phy_get_events_v2_hw()
1567 	err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);  in phy_get_events_v2_hw()
1570 	err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);  in phy_get_events_v2_hw()
1593 static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)  in sl_notify_ssp_v2_hw()  argument
1597 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);  in sl_notify_ssp_v2_hw()
1599 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);  in sl_notify_ssp_v2_hw()
1601 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);  in sl_notify_ssp_v2_hw()
1603 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);  in sl_notify_ssp_v2_hw()
1611 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,  in phy_set_linkrate_v2_hw()  argument
1618 	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,  in phy_set_linkrate_v2_hw()
2587 		int phy_no = sas_phy->id;  in hisi_sas_internal_abort_quirk_timeout()  local
2590 		link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);  in hisi_sas_internal_abort_quirk_timeout()
2595 			txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,  in hisi_sas_internal_abort_quirk_timeout()
2598 			hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,  in hisi_sas_internal_abort_quirk_timeout()
2636 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)  in phy_up_v2_hw()  argument
2640 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in phy_up_v2_hw()
2646 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);  in phy_up_v2_hw()
2648 	if (is_sata_phy_v2_hw(hisi_hba, phy_no))  in phy_up_v2_hw()
2653 	if (phy_no == 8) {  in phy_up_v2_hw()
2662 		port_id = (port_id >> (4 * phy_no)) & 0xf;  in phy_up_v2_hw()
2664 		link_rate = (link_rate >> (phy_no * 4)) & 0xf;  in phy_up_v2_hw()
2668 		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);  in phy_up_v2_hw()
2674 		u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,  in phy_up_v2_hw()
2682 	dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);  in phy_up_v2_hw()
2702 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,  in phy_up_v2_hw()
2704 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);  in phy_up_v2_hw()
2720 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)  in phy_down_v2_hw()  argument
2723 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in phy_down_v2_hw()
2728 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);  in phy_down_v2_hw()
2731 	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);  in phy_down_v2_hw()
2732 	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,  in phy_down_v2_hw()
2735 	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);  in phy_down_v2_hw()
2736 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,  in phy_down_v2_hw()
2743 	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);  in phy_down_v2_hw()
2744 	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,  in phy_down_v2_hw()
2747 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);  in phy_down_v2_hw()
2748 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);  in phy_down_v2_hw()
2757 	int phy_no = 0;  in int_phy_updown_v2_hw()  local
2764 			u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,  in int_phy_updown_v2_hw()
2772 				if (phy_up_v2_hw(phy_no, hisi_hba) ==  in int_phy_updown_v2_hw()
2779 				if (phy_down_v2_hw(phy_no, hisi_hba) ==  in int_phy_updown_v2_hw()
2788 				if (reg_value & BIT(phy_no)) {  in int_phy_updown_v2_hw()
2790 					if (phy_up_v2_hw(phy_no, hisi_hba) ==  in int_phy_updown_v2_hw()
2795 					if (phy_down_v2_hw(phy_no, hisi_hba) ==  in int_phy_updown_v2_hw()
2807 		phy_no++;  in int_phy_updown_v2_hw()
2813 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)  in phy_bcast_v2_hw()  argument
2815 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in phy_bcast_v2_hw()
2819 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);  in phy_bcast_v2_hw()
2820 	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);  in phy_bcast_v2_hw()
2825 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,  in phy_bcast_v2_hw()
2827 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);  in phy_bcast_v2_hw()
2862 	int phy_no = 0;  in int_chnl_int_v2_hw()  local
2873 		u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2875 		u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2877 		u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2880 		if ((irq_msk & (1 << phy_no)) && irq_value1) {  in int_chnl_int_v2_hw()
2891 					error->msg, phy_no, irq_value1);  in int_chnl_int_v2_hw()
2895 			hisi_sas_phy_write32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2899 		if ((irq_msk & (1 << phy_no)) && irq_value2) {  in int_chnl_int_v2_hw()
2900 			struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in int_chnl_int_v2_hw()
2904 					 phy_no);  in int_chnl_int_v2_hw()
2909 			hisi_sas_phy_write32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2913 		if ((irq_msk & (1 << phy_no)) && irq_value0) {  in int_chnl_int_v2_hw()
2915 				phy_bcast_v2_hw(phy_no, hisi_hba);  in int_chnl_int_v2_hw()
2918 				hisi_sas_phy_oob_ready(hisi_hba, phy_no);  in int_chnl_int_v2_hw()
2920 			hisi_sas_phy_write32(hisi_hba, phy_no,  in int_chnl_int_v2_hw()
2926 		irq_msk &= ~(1 << phy_no);  in int_chnl_int_v2_hw()
2927 		phy_no++;  in int_chnl_int_v2_hw()
3202 	int phy_no, offset;  in sata_int_v2_hw()  local
3206 	phy_no = sas_phy->id;  in sata_int_v2_hw()
3207 	initial_fis = &hisi_hba->initial_fis[phy_no];  in sata_int_v2_hw()
3210 	offset = 4 * (phy_no / 4);  in sata_int_v2_hw()
3213 			 ent_msk | 1 << ((phy_no % 4) * 8));  in sata_int_v2_hw()
3217 			     (phy_no % 4)));  in sata_int_v2_hw()
3218 	ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);  in sata_int_v2_hw()
3220 		dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);  in sata_int_v2_hw()
3227 		dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,  in sata_int_v2_hw()
3234 	if (unlikely(phy_no == 8)) {  in sata_int_v2_hw()
3243 		port_id = (port_id >> (4 * phy_no)) & 0xf;  in sata_int_v2_hw()
3245 		link_rate = (link_rate >> (phy_no * 4)) & 0xf;  in sata_int_v2_hw()
3249 		dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);  in sata_int_v2_hw()
3255 	hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,  in sata_int_v2_hw()
3264 	attached_sas_addr[7] = phy_no;  in sata_int_v2_hw()
3267 	dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);  in sata_int_v2_hw()
3327 	int i, phy_no, fatal_no, queue_no;  in interrupt_init_v2_hw()  local
3341 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {  in interrupt_init_v2_hw()
3342 		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];  in interrupt_init_v2_hw()
3344 		irq = hisi_hba->irq_map[phy_no + 72];  in interrupt_init_v2_hw()
3477 	int phy_no, count;  in write_gpio_v2_hw()  local
3487 		for (phy_no = 0; phy_no < count; phy_no++) {  in write_gpio_v2_hw()
3495 					reg_index * 4 + phy_no;  in write_gpio_v2_hw()
3496 			int data_idx = phy_no + 3 - (phy_no % 4) * 2;  in write_gpio_v2_hw()