372 			dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);  in tegra_pcie_rp_irq_handler()
411 		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);  in tegra_pcie_rp_irq_handler()
599 	dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);  in disable_aspm_l11()
608 	dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);  in disable_aspm_l12()
620 	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);  in event_counter_prog()
648 	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],  in aspm_state_cnt()
654 	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);  in aspm_state_cnt()
670 	dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);  in init_host_aspm()
677 	dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);  in init_host_aspm()
684 	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);  in init_host_aspm()
828 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);  in config_gen3_gen4_eq_presets()
834 	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);  in config_gen3_gen4_eq_presets()
839 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);  in config_gen3_gen4_eq_presets()
845 	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);  in config_gen3_gen4_eq_presets()
849 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);  in config_gen3_gen4_eq_presets()
866 	dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);  in tegra194_pcie_host_init()
871 	dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);  in tegra194_pcie_host_init()
873 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);  in tegra194_pcie_host_init()
880 	dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);  in tegra194_pcie_host_init()
886 	dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);  in tegra194_pcie_host_init()
900 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);  in tegra194_pcie_host_init()
905 		dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);  in tegra194_pcie_host_init()
979 		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);  in tegra194_pcie_start_link()
1748 		dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);  in pex_ep_event_pex_rst_deassert()
1763 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);  in pex_ep_event_pex_rst_deassert()
1771 	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);  in pex_ep_event_pex_rst_deassert()
1773 	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);  in pex_ep_event_pex_rst_deassert()