36 	void __iomem *mgmt_base;  member
87 	writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);  in fu740_pcie_assert_reset()
93 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);  in fu740_pcie_deassert_reset()
128 		phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;  in fu740_phyregwrite()
129 		phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;  in fu740_phyregwrite()
130 		phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;  in fu740_phyregwrite()
131 		phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;  in fu740_phyregwrite()
133 		phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;  in fu740_phyregwrite()
134 		phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;  in fu740_phyregwrite()
135 		phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;  in fu740_phyregwrite()
136 		phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;  in fu740_phyregwrite()
160 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);  in fu740_pcie_init_phy()
161 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);  in fu740_pcie_init_phy()
205 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);  in fu740_pcie_start_link()
260 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);  in fu740_pcie_host_init()
274 	writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);  in fu740_pcie_host_init()
278 	writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);  in fu740_pcie_host_init()
306 	afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");  in fu740_pcie_probe()
307 	if (IS_ERR(afp->mgmt_base))  in fu740_pcie_probe()
308 		return PTR_ERR(afp->mgmt_base);  in fu740_pcie_probe()