86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))  macro
185 		ECR_WRITE(p, oecr);  in change_mode()
191 	ECR_WRITE(p, oecr);  in change_mode()
255 		ECR_WRITE(p, s->u.pc.ecr);  in parport_pc_restore_state()
505 			ECR_WRITE(port, ecrval & ~(1<<2));  in parport_pc_fifo_write_block_pio()
1494 	ECR_WRITE(pb, 0x34);  in parport_ECR_present()
1574 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in parport_ECP_supported()
1575 	ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */  in parport_ECP_supported()
1584 		ECR_WRITE(pb, ECR_SPP << 5);  in parport_ECP_supported()
1635 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in parport_ECP_supported()
1636 	ECR_WRITE(pb, 0xf4); /* Configuration mode */  in parport_ECP_supported()
1696 			ECR_WRITE(pb, i);  in intel_bug_present_check_epp()
1704 		ECR_WRITE(pb, ecr);  in intel_bug_present_check_epp()
1735 	ECR_WRITE(pb, ECR_PS2 << 5);  in parport_ECPPS2_supported()
1737 	ECR_WRITE(pb, oecr);  in parport_ECPPS2_supported()
1788 	ECR_WRITE(pb, 0x80);  in parport_ECPEPP_supported()
1792 	ECR_WRITE(pb, oecr);  in parport_ECPEPP_supported()
1843 	ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */  in programmable_irq_support()
1848 	ECR_WRITE(pb, oecr);  in programmable_irq_support()
1859 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in irq_probe_ECP()
1860 	ECR_WRITE(pb, (ECR_TST << 5) | 0x04);  in irq_probe_ECP()
1861 	ECR_WRITE(pb, ECR_TST << 5);  in irq_probe_ECP()
1868 	ECR_WRITE(pb, ECR_SPP << 5);  in irq_probe_ECP()
1909 		ECR_WRITE(pb, oecr);  in irq_probe_EPP()
1979 	ECR_WRITE(p, oecr);  in programmable_dma_support()
2210 		ECR_WRITE(p, 0x34);  in parport_pc_probe_port()