Lines Matching refs:wlcore_write32
725 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr); in wl12xx_top_reg_write()
730 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val); in wl12xx_top_reg_write()
735 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE); in wl12xx_top_reg_write()
752 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr); in wl12xx_top_reg_read()
757 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ); in wl12xx_top_reg_read()
1017 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk); in wl127x_boot_clk()
1029 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause); in wl127x_boot_clk()
1042 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); in wl1271_boot_soft_reset()
1068 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0); in wl1271_boot_soft_reset()
1073 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff); in wl1271_boot_soft_reset()
1097 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); in wl12xx_pre_boot()
1122 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk); in wl12xx_pre_boot()
1153 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND); in wl12xx_pre_upload()
1205 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL); in wl12xx_enable_interrupts()
1507 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); in wl12xx_get_fuse_mac()