Lines Matching refs:GENMASK
10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
31 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
32 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
35 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
36 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
39 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
40 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
41 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
42 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
45 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
47 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
48 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
53 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
56 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
57 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
60 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
61 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
62 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
63 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
69 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
70 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
71 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
75 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
76 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
77 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
79 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
82 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
84 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
87 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
88 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
91 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
102 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
103 #define AX_RXD_SHIFT_MASK GENMASK(15, 14)
104 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
107 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
108 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
112 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
113 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
115 #define AX_RXD_USER_ID_MASK GENMASK(15, 8)
116 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
117 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
118 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
123 #define AX_RXD_BW_MASK GENMASK(31, 30)
124 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
127 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
144 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
145 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
146 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
152 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
159 #define AX_RXD_TID_MASK GENMASK(11, 8)
163 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
164 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
167 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
168 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
169 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
170 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
176 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
179 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
181 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
183 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
192 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28))
194 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24))
200 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16))
202 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14))
204 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0))
206 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30))
208 le32_get_bits((rxdesc)->dword1, GENMASK(31, 29))
210 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25))
212 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16))
214 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8))
218 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4))
220 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0))
222 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0))
236 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28))
238 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16))
240 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0))
244 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24))
246 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16))
248 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8))
250 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0))
253 le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0))
255 le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8))
257 le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16))
263 le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30))
265 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0))
267 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16))
279 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8))
282 le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0))
284 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0))
286 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8))
288 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16))
290 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24))
292 le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8))
294 le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24))
296 le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0))
298 le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5))
300 le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16))
302 le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20))