Lines Matching refs:GENMASK

12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
46 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
48 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
49 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
52 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
55 #define B_AX_OCP_L1_MASK GENMASK(15, 13)
58 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
61 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
62 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
67 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
87 #define B_AX_BTMODE_MASK GENMASK(7, 6)
95 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
98 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
100 #define B_AX_DBG_SEL1 GENMASK(23, 16)
101 #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
103 #define B_AX_DBG_SEL0 GENMASK(7, 0)
122 #define B_AX_R_AX_BG GENMASK(1, 0)
134 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
135 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
141 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
147 #define B_AX_CHIP_VER_MASK GENMASK(15, 12)
150 #define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
151 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
165 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
174 #define PS_RPWM_SEQ_NUM GENMASK(13, 12)
178 #define PS_CPWM_SEQ_NUM GENMASK(13, 12)
179 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
180 #define PS_CPWM_STATE GENMASK(2, 0)
184 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
202 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
205 #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
206 #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
207 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
211 #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
212 #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
213 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
230 #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
231 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
232 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
233 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
234 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
235 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
238 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
240 #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
245 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
246 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
247 #define B_AX_DMA_MODE_MASK GENMASK(19, 18)
256 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
260 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
292 #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
293 #define B_AX_DBG_SEL_MASK GENMASK(15, 13)
313 #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
315 #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
317 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
319 #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
324 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
468 #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
469 #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
477 #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
478 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
485 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
521 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
904 #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
905 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
906 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
907 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
909 #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
913 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
914 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
916 #define B_AX_MAX_PG_MASK GENMASK(28, 16)
917 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
932 #define B_AX_AVAL_PG_MASK GENMASK(27, 16)
933 #define B_AX_USE_PG_MASK GENMASK(12, 0)
949 #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
950 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
953 #define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
954 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
957 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
960 #define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
961 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
964 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
967 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
968 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
971 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
974 #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
977 #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
978 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
979 #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
982 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1143 #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
1144 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1151 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1152 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1153 #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
1154 #define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
1155 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1156 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1164 #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
1165 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1167 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1170 #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
1171 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1172 #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1295 #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
1296 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1304 #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
1305 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1318 #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
1319 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1321 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1324 #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
1325 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1328 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1329 #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
1330 #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
1331 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1334 #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
1335 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1442 #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
1443 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1448 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1453 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1454 #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
1455 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1459 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1460 #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
1461 #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
1462 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1466 #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
1467 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1472 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1530 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1568 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1588 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1589 #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
1590 #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
1592 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1596 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1600 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1604 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1608 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1660 #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
1661 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1663 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1667 #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1670 #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1671 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1674 #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1676 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1716 #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1718 #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1719 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1722 #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1723 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1793 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
1804 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
1825 #define B_AX_TXSC_80M_MASK GENMASK(11, 8)
1826 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
1827 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
1838 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
1839 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
1856 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
1861 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
1866 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
1871 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
1876 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
1880 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
1881 #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
1882 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
1883 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
1914 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
1918 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
1919 #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
1920 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
1965 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
1977 #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
1978 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
1982 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
1998 #define B_AX_NET_TYPE_MASK GENMASK(11, 10)
2015 #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
2016 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2023 #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
2024 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2031 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2038 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2045 #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
2052 #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
2053 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2060 #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
2061 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2062 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2069 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2070 #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
2071 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2072 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2092 #define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
2093 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2100 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2107 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2114 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2121 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2125 #define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
2126 #define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
2150 #define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
2161 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2162 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
2163 #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
2164 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2168 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2169 #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
2170 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2175 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2176 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
2179 #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
2180 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2185 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2187 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2194 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2195 #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
2200 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2201 #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
2202 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2206 #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
2209 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2210 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2212 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2218 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2232 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2233 #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
2234 #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
2235 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2239 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2293 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2301 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2305 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2449 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2451 #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
2453 #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
2467 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2470 #define B_AX_TCR_USTIME GENMASK(23, 16)
2475 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
2476 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2480 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2481 #define B_AX_STMP_THSD_MASK GENMASK(15, 8)
2490 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2491 #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
2492 #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
2494 #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
2496 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2497 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2501 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2502 #define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
2507 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2511 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2515 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2519 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2531 #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
2532 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2549 #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
2550 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
2563 #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
2566 #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
2568 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
2572 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2575 #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
2577 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
2582 #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
2612 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
2616 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
2620 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
2637 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
2649 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
2653 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
2687 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
2700 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
2701 #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
2702 #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
2708 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
2709 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
2710 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
2724 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
2729 #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
2736 #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
2737 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
2738 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
2739 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
2740 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
2748 #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
2749 #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
2750 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
2758 #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
2759 #define B_AX_CH_EN_MASK GENMASK(3, 0)
2763 #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
2764 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
2779 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
2781 #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
2782 #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
2789 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
2817 #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
2818 #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
2827 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
2851 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
2852 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
2853 #define B_AX_STATE_NXT_MASK GENMASK(13, 8)
2855 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
2924 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
2925 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
2926 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
2930 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
2935 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
2940 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
2944 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
2949 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
2950 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
2952 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
2953 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3012 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3025 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3028 #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
3032 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3041 #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
3042 #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
3043 #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
3044 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3045 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3077 #define B_AX_TIMER_MASK GENMASK(7, 0)
3083 #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
3085 #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
3087 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3097 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3098 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3100 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3101 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3130 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3131 #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
3132 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3142 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3143 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3181 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3183 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3199 #define RR_MOD_IQK GENMASK(19, 4)
3200 #define RR_MOD_DPK GENMASK(19, 5)
3201 #define RR_MOD_MASK GENMASK(19, 16)
3210 #define RR_MOD_NBW GENMASK(15, 14)
3211 #define RR_MOD_M_RXG GENMASK(13, 4)
3212 #define RR_MOD_M_RXBB GENMASK(9, 5)
3214 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
3216 #define RR_WLSEL_AG GENMASK(18, 16)
3224 #define RR_LOKVB_COI GENMASK(19, 14)
3225 #define RR_LOKVB_COQ GENMASK(9, 4)
3227 #define RR_TXIG_TG GENMASK(16, 12)
3228 #define RR_TXIG_GR1 GENMASK(6, 4)
3229 #define RR_TXIG_GR0 GENMASK(1, 0)
3231 #define RR_CHTR_MOD GENMASK(11, 10)
3232 #define RR_CHTR_TXRX GENMASK(9, 0)
3235 #define RR_CFGCH_BAND1 GENMASK(17, 16)
3239 #define RR_CFGCH_BAND0 GENMASK(9, 8)
3243 #define RR_CFGCH_BW GENMASK(11, 10)
3244 #define RR_CFGCH_CH GENMASK(7, 0)
3250 #define RR_APK_MOD GENMASK(5, 4)
3252 #define RR_BTC_TXBB GENMASK(14, 12)
3253 #define RR_BTC_RXBB GENMASK(11, 10)
3255 #define RR_RCKC_CA GENMASK(14, 10)
3258 #define RR_RCKO_OFF GENMASK(13, 9)
3260 #define RR_RXKPLL_OFF GENMASK(5, 0)
3263 #define RR_RSV4_AGH GENMASK(17, 16)
3264 #define RR_RSV4_PLLCH GENMASK(9, 0)
3270 #define RR_LUTWA_MASK GENMASK(9, 0)
3271 #define RR_LUTWA_M2 GENMASK(4, 0)
3274 #define RR_LUTWD0_LB GENMASK(5, 0)
3277 #define RR_TM_VAL GENMASK(6, 1)
3279 #define RR_TM2_OFF GENMASK(19, 16)
3288 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
3291 #define RR_GAINTX_ALL GENMASK(15, 0)
3292 #define RR_GAINTX_PAD GENMASK(9, 5)
3293 #define RR_GAINTX_BB GENMASK(4, 0)
3295 #define RR_TXMO_COI GENMASK(19, 15)
3296 #define RR_TXMO_COQ GENMASK(14, 10)
3297 #define RR_TXMO_FII GENMASK(9, 6)
3298 #define RR_TXMO_FIQ GENMASK(5, 2)
3300 #define RR_TXA_TRK GENMASK(19, 14)
3306 #define RR_BIASA_TXG GENMASK(15, 12)
3307 #define RR_BIASA_TXA GENMASK(19, 16)
3308 #define RR_BIASA_A GENMASK(2, 0)
3310 #define RR_BIASA2_LB GENMASK(4, 2)
3312 #define RR_TXATANK_LBSW2 GENMASK(17, 15)
3313 #define RR_TXATANK_LBSW GENMASK(16, 15)
3315 #define RR_TXA2_LDO GENMASK(19, 16)
3323 #define RR_RXPOW_IQK GENMASK(17, 16)
3325 #define RR_RXBB_VOBUF GENMASK(15, 12)
3326 #define RR_RXBB_C2G GENMASK(16, 10)
3327 #define RR_RXBB_C1G GENMASK(9, 8)
3328 #define RR_RXBB_ATTR GENMASK(7, 4)
3329 #define RR_RXBB_ATTC GENMASK(2, 0)
3331 #define RR_RXG_IQKMOD GENMASK(19, 16)
3333 #define RR_XGLNA2_SW GENMASK(1, 0)
3335 #define RR_RXAE_IQKMOD GENMASK(3, 0)
3337 #define RR_RXA_DPK GENMASK(9, 8)
3339 #define RR_RXA2_C1 GENMASK(12, 10)
3340 #define RR_RXA2_C2 GENMASK(9, 3)
3341 #define RR_RXA2_IATT GENMASK(7, 4)
3342 #define RR_RXA2_ATT GENMASK(3, 0)
3344 #define RR_RXIQGEN_ATTL GENMASK(12, 8)
3345 #define RR_RXIQGEN_ATTH GENMASK(14, 13)
3349 #define RR_EN_TIA_IDA GENMASK(11, 10)
3350 #define RR_RXBB2_IDAC GENMASK(11, 9)
3351 #define RR_RXBB2_EBW GENMASK(6, 5)
3353 #define RR_XALNA2_SW GENMASK(1, 0)
3355 #define RR_DCK_DONE GENMASK(7, 5)
3359 #define RR_DCK1_CLR GENMASK(3, 0)
3362 #define RR_DCK2_CYCLE GENMASK(7, 2)
3366 #define RR_IQGEN_BIAS GENMASK(11, 8)
3368 #define RR_TXIQK_ATT2 GENMASK(15, 12)
3372 #define RR_MIXER_GN GENMASK(4, 3)
3374 #define RR_LOGEN_RPT GENMASK(19, 16)
3380 #define RR_IQKPLL_MOD GENMASK(9, 8)
3382 #define RR_RCKD_POW GENMASK(19, 13)
3401 #define B_ANAPAR_PW15 GENMASK(31, 24)
3402 #define B_ANAPAR_PW15_H GENMASK(27, 24)
3403 #define B_ANAPAR_PW15_H2 GENMASK(27, 26)
3405 #define B_ANAPAR_15 GENMASK(31, 16)
3408 #define B_ANAPAR_CRXBB GENMASK(18, 16)
3409 #define B_ANAPAR_14 GENMASK(15, 0)
3415 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
3416 #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
3417 #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
3420 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
3422 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
3423 #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
3424 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
3426 #define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
3432 #define B_CH_IDX_SEG0 GENMASK(23, 16)
3437 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
3457 #define B_PMAC_GNT_P1 GENMASK(20, 17)
3458 #define B_PMAC_GNT_P2 GENMASK(29, 26)
3460 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
3462 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
3467 #define B_MAC_SEL_MOD GENMASK(4, 2)
3471 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
3475 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
3481 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
3486 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
3487 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
3491 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
3493 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
3495 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
3497 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
3499 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
3501 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
3503 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
3505 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
3515 #define B_SNDCCA_A1_EN GENMASK(19, 12)
3517 #define B_SNDCCA_A2_VAL GENMASK(19, 12)
3519 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
3521 #define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
3525 #define B_RXHETB_MAX_NSS GENMASK(25, 23)
3526 #define B_RXHE_MAX_NSS GENMASK(16, 14)
3527 #define B_RXHE_USER_MAX GENMASK(13, 6)
3537 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3540 #define B_P0_TXCK_ALL GENMASK(19, 12)
3542 #define B_P0_RXCK_VAL GENMASK(18, 16)
3544 #define B_P0_TXCK_VAL GENMASK(14, 12)
3548 #define B_S0_RXDC_I GENMASK(25, 16)
3549 #define B_S0_RXDC_Q GENMASK(31, 26)
3551 #define B_S0_RXDC2_SEL GENMASK(9, 8)
3552 #define B_S0_RXDC2_AVG GENMASK(7, 6)
3553 #define B_S0_RXDC2_MEN GENMASK(5, 4)
3554 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
3565 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
3566 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
3568 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
3569 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
3571 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
3572 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
3574 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
3575 #define B_IFS_T3_HIS_MSK GENMASK(23, 16)
3576 #define B_IFS_T2_HIS_MSK GENMASK(15, 8)
3577 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
3579 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
3580 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
3582 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
3583 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
3585 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
3586 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
3588 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
3589 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
3592 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
3594 #define B_TXAGC_TP GENMASK(2, 0)
3596 #define B_TSSI_THER GENMASK(29, 24)
3598 #define B_TXAGC_BTP GENMASK(31, 24)
3600 #define B_TXAGC_BB_OFT GENMASK(31, 16)
3601 #define B_TXAGC_BB GENMASK(31, 24)
3603 #define B_S0_ADDCK_I GENMASK(9, 0)
3604 #define B_S0_ADDCK_Q GENMASK(19, 10)
3606 #define B_ADC_FIFO_RST GENMASK(31, 24)
3607 #define B_ADC_FIFO_RXK GENMASK(31, 16)
3613 #define B_TXFIR_C01 GENMASK(23, 0)
3615 #define B_TXFIR_C23 GENMASK(23, 0)
3617 #define B_TXFIR_C45 GENMASK(23, 0)
3619 #define B_TXFIR_C67 GENMASK(23, 0)
3621 #define B_TXFIR_C89 GENMASK(23, 0)
3623 #define B_TXFIR_CAB GENMASK(23, 0)
3625 #define B_TXFIR_CCD GENMASK(23, 0)
3627 #define B_TXFIR_CEF GENMASK(23, 0)
3631 #define B_RPL_OFST_MASK GENMASK(14, 8)
3639 #define B_RXSCOBC_TH GENMASK(18, 0)
3641 #define B_RXSCOCCK_TH GENMASK(18, 0)
3650 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3654 #define B_S1_RXDC_I GENMASK(25, 16)
3655 #define B_S1_RXDC_Q GENMASK(31, 26)
3657 #define B_S1_RXDC2_EN GENMASK(5, 4)
3658 #define B_S1_RXDC2_SEL GENMASK(9, 8)
3659 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
3661 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
3662 #define B_TXAGC_BB_S1 GENMASK(31, 24)
3664 #define B_S1_ADDCK_I GENMASK(9, 0)
3665 #define B_S1_ADDCK_Q GENMASK(19, 10)
3667 #define B_DCFO GENMASK(1, 0)
3669 #define B_SEG0CSI_IDX GENMASK(11, 0)
3674 #define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
3675 #define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
3678 #define B_CFO_TRK_MSK GENMASK(14, 10)
3686 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
3688 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
3694 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
3696 #define B_TXPWR_MSK GENMASK(30, 22)
3698 #define B_TXNSS_MAP_MSK GENMASK(20, 17)
3700 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
3702 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
3704 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
3706 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
3708 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
3710 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
3712 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
3714 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
3716 #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
3718 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
3719 #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
3720 #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
3722 #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
3723 #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
3724 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
3726 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
3727 #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
3728 #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
3729 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
3731 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
3732 #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
3733 #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
3735 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
3737 #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
3738 #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
3740 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
3741 #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
3742 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
3744 #define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
3746 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
3748 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
3750 #define B_PATH0_BTG_SHEN GENMASK(18, 17)
3758 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3760 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
3762 #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
3763 #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
3773 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
3776 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
3779 #define B_P1_MODE_SEL GENMASK(31, 30)
3783 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
3787 #define B_PATH1_BTG_SHEN GENMASK(18, 17)
3789 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
3791 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3797 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
3799 #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
3807 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
3811 #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
3815 #define B_FC0_BW_INV GENMASK(6, 0)
3816 #define B_FC0_BW_SET GENMASK(31, 30)
3817 #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
3818 #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
3819 #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
3822 #define B_CHBW_MOD_SBW GENMASK(13, 12)
3823 #define B_CHBW_MOD_PRICH GENMASK(11, 8)
3824 #define B_ANT_RX_SEG0 GENMASK(3, 0)
3828 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
3830 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
3832 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
3836 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
3838 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
3840 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
3842 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
3844 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
3847 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
3850 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
3855 #define B_PATH0_5MDET_TH GENMASK(5, 0)
3857 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
3860 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
3863 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
3868 #define B_PATH1_5MDET_TH GENMASK(5, 0)
3870 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
3872 #define B_RPL_PATHB_MASK GENMASK(23, 16)
3873 #define B_RPL_PATHA_MASK GENMASK(15, 8)
3875 #define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
3876 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
3878 #define B_FC0_MSK_V1 GENMASK(12, 0)
3882 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
3884 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
3891 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
3892 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
3895 #define B_ACK_VAL GENMASK(30, 29)
3901 #define B_TXPWRB_VAL GENMASK(27, 19)
3905 #define B_DPD_OFT_ADDR GENMASK(31, 27)
3909 #define B_P0_TMETER GENMASK(15, 10)
3915 #define B_P0_TSSI_OFT GENMASK(7, 0)
3917 #define B_P0_TSSI_AVG GENMASK(15, 12)
3919 #define B_P0_RFCTM_VAL GENMASK(25, 20)
3925 #define B_P0_TRSW_SO_A2 GENMASK(7, 5)
3930 #define B_P0_RFM_OUT GENMASK(4, 0)
3932 #define B_P0_TXDPD GENMASK(31, 28)
3937 #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
3940 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
3943 #define B_S0_DACKI_AR GENMASK(31, 28)
3946 #define B_S0_DACKI2_K GENMASK(21, 12)
3948 #define B_S0_DACKI7_K GENMASK(15, 8)
3950 #define B_S0_DACKI8_K GENMASK(15, 8)
3952 #define B_S0_DACKQ_AR GENMASK(31, 28)
3955 #define B_S0_DACKQ2_K GENMASK(21, 12)
3957 #define B_S0_DACKQ7_K GENMASK(15, 8)
3959 #define B_S0_DACKQ8_K GENMASK(15, 8)
3961 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
3963 #define B_P1_TMETER GENMASK(15, 10)
3969 #define B_P1_TSSI_OFT GENMASK(7, 0)
3971 #define B_P1_TSSI_AVG GENMASK(15, 12)
3974 #define B_P1_RFCTM_VAL GENMASK(25, 20)
3979 #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
3982 #define B_S1_DACKI_AR GENMASK(31, 28)
3985 #define B_S1_DACKI2_K GENMASK(21, 12)
3987 #define B_S1_DACKI_K GENMASK(15, 8)
3989 #define B_S1_DACKI8_K GENMASK(15, 8)
3991 #define B_S1_DACKQ_AR GENMASK(31, 28)
3994 #define B_S1_DACKQ2_K GENMASK(21, 12)
3996 #define B_S1_DACKQ7_K GENMASK(15, 8)
3998 #define B_S1_DACKQ8_K GENMASK(15, 8)
4000 #define B_NCTL_CFG_SPAGE GENMASK(2, 1)
4004 #define B_NCTL_N1_CIP GENMASK(7, 0)
4008 #define B_IQK_DIF_TRX GENMASK(1, 0)
4010 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
4012 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
4014 #define B_IQK_DIF4_RXT GENMASK(27, 16)
4015 #define B_IQK_DIF4_TXT GENMASK(11, 0)
4018 #define B_IQK_CFG_SET GENMASK(5, 4)
4021 #define B_TPG_MOD_F GENMASK(2, 1)
4024 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
4028 #define B_KIP_MOD GENMASK(19, 0)
4036 #define B_LDL_NORM_PN GENMASK(12, 8)
4037 #define B_LDL_NORM_OP GENMASK(1, 0)
4041 #define B_DPK_CFG_IDX GENMASK(14, 12)
4046 #define B_KPATH_CFG_ED GENMASK(21, 20)
4048 #define B_KIP_RPT1_SEL GENMASK(21, 16)
4063 #define B_PRT_COM_DCI GENMASK(27, 16)
4064 #define B_PRT_COM_CORV GENMASK(15, 8)
4065 #define B_PRT_COM_DCQ GENMASK(11, 0)
4067 #define B_PRT_COM_GL GENMASK(7, 4)
4068 #define B_PRT_COM_CORI GENMASK(7, 0)
4069 #define B_PRT_COM_RXBB GENMASK(5, 0)
4076 #define B_IQK_RES_TXCFIR GENMASK(11, 8)
4077 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
4082 #define B_RXIQC_NEWP GENMASK(19, 8)
4083 #define B_RXIQC_NEWX GENMASK(31, 20)
4088 #define B_RFGAIN_PAD GENMASK(4, 0)
4089 #define B_RFGAIN_TXBB GENMASK(12, 8)
4091 #define B_RFGAIN_BND GENMASK(4, 0)
4098 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
4099 #define B_CFIR_LUT_GP GENMASK(1, 0)
4101 #define B_DPK_GN_EN GENMASK(17, 16)
4102 #define B_DPK_GN_AG GENMASK(9, 0)
4108 #define B_DPD_MEN GENMASK(31, 28)
4109 #define B_DPD_ORDER GENMASK(26, 24)
4110 #define B_DPD_SEL GENMASK(13, 8)
4112 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
4115 #define B_KIP_IQP_SW GENMASK(13, 12)
4116 #define B_KIP_IQP_IQSW GENMASK(5, 0)
4118 #define B_KIP_RPT_SEL GENMASK(21, 16)
4122 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
4126 #define B_DPK_GL_A0 GENMASK(31, 28)
4127 #define B_DPK_GL_A1 GENMASK(17, 0)
4129 #define B_RPT_PER_TSSI GENMASK(28, 16)
4130 #define B_RPT_PER_OF GENMASK(15, 8)
4131 #define B_RPT_PER_TH GENMASK(5, 0)
4149 #define B_IQKINF_VER GENMASK(31, 24)
4150 #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
4151 #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
4152 #define B_IQKINF_FAIL GENMASK(3, 0)
4158 #define B_IQKCH_CH GENMASK(15, 8)
4159 #define B_IQKCH_BW GENMASK(7, 4)
4160 #define B_IQKCH_BAND GENMASK(3, 0)
4162 #define B_IQKINF2_FCNT GENMASK(23, 16)
4163 #define B_IQKINF2_KCNT GENMASK(15, 8)
4164 #define B_IQKINF2_NCTLV GENMASK(7, 0)
4166 #define B_DCOF0_V GENMASK(4, 1)
4170 #define B_DCOF8_V GENMASK(4, 1)
4174 #define B_DACK_BIAS00 GENMASK(11, 2)
4176 #define B_DACK_S0M0 GENMASK(31, 24)
4179 #define B_DACK_DADCK00 GENMASK(31, 24)
4183 #define B_DACK_BIAS01 GENMASK(11, 2)
4185 #define B_DACK_S0M1 GENMASK(31, 24)
4188 #define B_DACK_DADCK01 GENMASK(31, 24)
4192 #define B_DRCK_VAL GENMASK(4, 0)
4194 #define B_DRCK_RES GENMASK(19, 15)
4197 #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4199 #define B_P0_CFCH_BW0 GENMASK(27, 26)
4201 #define B_P0_CFCH_BW1 GENMASK(8, 5)
4203 #define B_ADDCK0 GENMASK(9, 8)
4207 #define B_ADDCK0_RLS GENMASK(29, 28)
4208 #define B_ADDCK0_RL1 GENMASK(27, 18)
4209 #define B_ADDCK0_RL0 GENMASK(17, 8)
4211 #define B_ADDCKR0_A0 GENMASK(19, 10)
4212 #define B_ADDCKR0_A1 GENMASK(9, 0)
4214 #define B_DACK10 GENMASK(4, 1)
4218 #define B_DACK11 GENMASK(4, 1)
4222 #define B_DACK_BIAS10 GENMASK(11, 2)
4224 #define B_DACK10S GENMASK(31, 24)
4228 #define B_DACK_DADCK10 GENMASK(31, 24)
4232 #define B_DACK_BIAS11 GENMASK(11, 2)
4234 #define B_DACK11S GENMASK(31, 24)
4238 #define B_DACK_DADCK11 GENMASK(31, 24)
4240 #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4242 #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
4244 #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
4246 #define B_ADDCK1 GENMASK(9, 8)
4250 #define B_ADDCK1_RLS GENMASK(29, 28)
4251 #define B_ADDCK1_RL1 GENMASK(27, 18)
4252 #define B_ADDCK1_RL0 GENMASK(17, 8)
4254 #define B_ADDCKR1_A0 GENMASK(19, 10)
4255 #define B_ADDCKR1_A1 GENMASK(9, 0)
4265 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)