Lines Matching refs:GENMASK
135 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
137 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
139 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
141 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
143 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
153 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
165 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
167 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
172 #define XCAP_MASK GENMASK(6, 0)
180 #define BIT_ANT_PATH GENMASK(1, 0)
183 #define BIT_EDCCA_OPTION GENMASK(30, 29)
188 #define BITS_SUBTUNE GENMASK(15, 12)
207 #define BIT_3WIRE_EN GENMASK(1, 0)
216 #define BITS_RXAGC_CCK GENMASK(15, 12)
217 #define BITS_RXAGC_OFDM GENMASK(8, 4)
224 #define BIT_BBMODE GENMASK(2, 1)
246 #define BIT_SEL_PATH GENMASK(2, 1)
247 #define BIT_SUBPAGE GENMASK(3, 0)
249 #define BIT_GS_PWSF GENMASK(27, 0)
255 #define BIT_TX_CFIR GENMASK(31, 30)
256 #define BIT_CFIR_EN GENMASK(26, 24)
261 #define BIT_GLOSS_DB GENMASK(14, 12)
266 #define BIT_I_GAIN GENMASK(19, 16)
268 #define BIT_Q_GAIN_SEL GENMASK(14, 12)
269 #define BIT_Q_GAIN GENMASK(11, 0)
271 #define BIT_GAPK_RPT_IDX GENMASK(11, 8)
277 #define BIT_IQ_SWITCH GENMASK(5, 0)
282 #define BIT_RPT_SEL GENMASK(20, 16)
283 #define BIT_DPD_CLK GENMASK(7, 4)
289 #define BIT_RPT_DGAIN GENMASK(27, 16)
290 #define BIT_GAPK_RPT0 GENMASK(3, 0)
291 #define BIT_GAPK_RPT1 GENMASK(7, 4)
292 #define BIT_GAPK_RPT2 GENMASK(11, 8)
293 #define BIT_GAPK_RPT3 GENMASK(15, 12)
294 #define BIT_GAPK_RPT4 GENMASK(19, 16)
295 #define BIT_GAPK_RPT5 GENMASK(23, 20)
296 #define BIT_GAPK_RPT6 GENMASK(27, 24)
297 #define BIT_GAPK_RPT7 GENMASK(31, 28)
317 #define BIT_CCA_ON_BY_PW GENMASK(11, 3)
323 #define BIT_ANTSEG GENMASK(3, 0)
327 #define BIT_STOP_TX GENMASK(3, 0)
338 #define BIT_RPT_CIP_STATUS GENMASK(7, 0)
354 #define BIT_RF_MODE GENMASK(19, 16)
355 #define BIT_RXAGC GENMASK(9, 5)
356 #define BIT_TXAGC GENMASK(4, 0)
360 #define BIT_BW_TXBB GENMASK(14, 12)
361 #define BIT_BW_RXBB GENMASK(11, 10)
364 #define BIT_BB_GAIN GENMASK(18, 14)
365 #define BIT_RF_GAIN GENMASK(4, 2)
367 #define BIT_GAIN_TXBB GENMASK(4, 0)
369 #define BIT_TX_MODE GENMASK(19, 8)
371 #define BIT_GAIN_TX_PAD_H GENMASK(11, 8)
372 #define BIT_GAIN_TX_PAD_L GENMASK(7, 4)
374 #define RF_PABIAS_2G_MASK GENMASK(15, 12)
375 #define RF_PABIAS_5G_MASK GENMASK(19, 16)
377 #define BIT_TXA_LB_ATT GENMASK(15, 14)
378 #define BIT_LB_SW GENMASK(13, 12)
379 #define BIT_LB_ATT GENMASK(4, 2)
383 #define BIT_RXA_MIX_GAIN GENMASK(4, 3)
395 #define RF_THEMAL_MASK GENMASK(19, 16)
397 #define PPG_2G_A_MASK GENMASK(3, 0)
398 #define PPG_2G_B_MASK GENMASK(7, 4)
402 #define PPG_PABIAS_MASK GENMASK(3, 0)
405 #define PPG_5G_MASK GENMASK(4, 0)