Lines Matching refs:FIELD32
63 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
64 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
73 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
74 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
75 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
82 #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002)
88 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
89 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
90 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
91 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
92 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
93 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
94 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
95 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
96 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
97 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
103 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
104 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
105 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
106 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
107 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
108 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
109 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
110 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
111 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
112 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
182 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
183 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
184 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
185 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
222 #define MAC_CSR0_REVISION FIELD32(0x0000000f)
223 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
232 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
233 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
234 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
240 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
241 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
242 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
243 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
254 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
255 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
256 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
262 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
263 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
264 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
265 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
279 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
280 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
281 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
287 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
299 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
300 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
301 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
311 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
312 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
313 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
314 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
328 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
329 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
330 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
331 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
340 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
341 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
342 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
343 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
351 #define MAC_CSR13_VAL0 FIELD32(0x00000001)
352 #define MAC_CSR13_VAL1 FIELD32(0x00000002)
353 #define MAC_CSR13_VAL2 FIELD32(0x00000004)
354 #define MAC_CSR13_VAL3 FIELD32(0x00000008)
355 #define MAC_CSR13_VAL4 FIELD32(0x00000010)
356 #define MAC_CSR13_VAL5 FIELD32(0x00000020)
357 #define MAC_CSR13_DIR0 FIELD32(0x00000100)
358 #define MAC_CSR13_DIR1 FIELD32(0x00000200)
359 #define MAC_CSR13_DIR2 FIELD32(0x00000400)
360 #define MAC_CSR13_DIR3 FIELD32(0x00000800)
361 #define MAC_CSR13_DIR4 FIELD32(0x00001000)
362 #define MAC_CSR13_DIR5 FIELD32(0x00002000)
373 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
374 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
375 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
376 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
377 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
378 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
406 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
407 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
408 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
409 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
410 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
411 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
412 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
413 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
414 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
415 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
416 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
417 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
418 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
419 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
425 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
426 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
427 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
428 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
429 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
430 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
431 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
432 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
438 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
439 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
440 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
441 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
442 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
443 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
444 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
445 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
451 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
452 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
453 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
454 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
455 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
456 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
457 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
458 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
468 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
469 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
470 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
471 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
472 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
473 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
474 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
475 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
476 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
477 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
493 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
494 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
495 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
496 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
502 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
503 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
504 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
505 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
515 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
516 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
517 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
518 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
519 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
520 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
536 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
542 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
563 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
564 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
584 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
585 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
586 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
587 #define PHY_CSR3_BUSY FIELD32(0x00010000)
598 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
599 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
600 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
601 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
602 #define PHY_CSR4_BUSY FIELD32(0x80000000)
608 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
614 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
629 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
630 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
631 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
632 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
633 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
634 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
635 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
636 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
637 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
638 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
639 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
640 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
641 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
642 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
643 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
644 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
650 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
651 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
652 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
653 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
654 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
655 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
656 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
657 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
671 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
672 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
673 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
674 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
680 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
681 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
682 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
683 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
684 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
685 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
686 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
687 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
697 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
698 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
704 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
705 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
711 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
712 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
718 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
725 #define STA_CSR4_VALID FIELD32(0x00000001)
726 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
727 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
728 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
729 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
730 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
740 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
741 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
742 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
743 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
749 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
750 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
778 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
784 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
790 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
796 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
802 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
808 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
809 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
810 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
811 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
818 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
819 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
820 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
830 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
831 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
832 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
833 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
843 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
844 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
845 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
846 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
856 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
857 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
858 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
859 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
866 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
867 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
868 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
869 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
870 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
884 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
885 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
886 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
887 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
888 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
889 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
890 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
891 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
892 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
893 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
899 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
900 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
901 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
902 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
903 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
918 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
925 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
926 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
927 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
933 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
934 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
956 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
957 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
958 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
959 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
960 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
961 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
962 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
963 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
964 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
965 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
972 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
973 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
974 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
975 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
976 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
977 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
978 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
979 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
980 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
981 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
982 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
983 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
992 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
993 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
994 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
995 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
996 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
997 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
998 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1006 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1007 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1015 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1016 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1053 #define IO_CNTL_CSR_RF_PS FIELD32(0x00000004)
1130 #define RF3_TXPOWER FIELD32(0x00003e00)
1135 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1299 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1300 #define TXD_W0_VALID FIELD32(0x00000002)
1301 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1302 #define TXD_W0_ACK FIELD32(0x00000008)
1303 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1304 #define TXD_W0_OFDM FIELD32(0x00000020)
1305 #define TXD_W0_IFS FIELD32(0x00000040)
1306 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1307 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1308 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1309 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1310 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1311 #define TXD_W0_BURST FIELD32(0x10000000)
1312 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1320 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1321 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1322 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1323 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1324 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1325 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1326 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1327 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1332 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1333 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1334 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1335 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1340 #define TXD_W3_IV FIELD32(0xffffffff)
1345 #define TXD_W4_EIV FIELD32(0xffffffff)
1355 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1356 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1357 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1358 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1359 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1374 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1375 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1376 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1377 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1378 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1383 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1384 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1385 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1386 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1387 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1392 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1397 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1408 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1409 #define RXD_W0_DROP FIELD32(0x00000002)
1410 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1411 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1412 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1413 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1414 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1415 #define RXD_W0_OFDM FIELD32(0x00000080)
1416 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1417 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1418 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1419 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1425 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1426 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1427 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1428 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1434 #define RXD_W2_IV FIELD32(0xffffffff)
1440 #define RXD_W3_EIV FIELD32(0xffffffff)
1447 #define RXD_W4_ICV FIELD32(0xffffffff)
1459 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1464 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1465 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1466 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1467 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1468 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1469 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1470 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1471 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1472 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1473 #define RXD_W15_RESERVED FIELD32(0xffffffff)