Lines Matching refs:GENMASK
12 #define MT_RXD0_LENGTH GENMASK(15, 0)
13 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
16 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
33 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
39 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
40 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
52 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
55 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
57 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
58 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
72 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
74 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
92 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
93 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
98 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
100 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
101 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
103 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
106 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
107 #define MT_RXD6_TA_LO GENMASK(31, 16)
109 #define MT_RXD7_TA_HI GENMASK(31, 0)
111 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
112 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
114 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
117 #define MT_PRXV_TX_RATE GENMASK(6, 0)
120 #define MT_PRXV_NSTS GENMASK(9, 7)
123 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
124 #define MT_PRXV_SGI GENMASK(16, 15)
125 #define MT_PRXV_STBC GENMASK(23, 22)
126 #define MT_PRXV_TX_MODE GENMASK(27, 24)
127 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
130 #define MT_PRXV_RCPI3 GENMASK(31, 24)
131 #define MT_PRXV_RCPI2 GENMASK(23, 16)
132 #define MT_PRXV_RCPI1 GENMASK(15, 8)
133 #define MT_PRXV_RCPI0 GENMASK(7, 0)
134 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
137 #define MT_CRXV_HT_STBC GENMASK(1, 0)
138 #define MT_CRXV_TX_MODE GENMASK(7, 4)
139 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
140 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
141 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
144 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
147 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
148 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
149 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
150 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
151 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
153 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
154 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
155 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
156 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
158 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
159 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
163 #define MT_CRXV_SNR GENMASK(18, 13)
164 #define MT_CRXV_FOE_LO GENMASK(31, 19)
165 #define MT_CRXV_FOE_HI GENMASK(6, 0)
208 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
209 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
210 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
212 #define MT_TX_FREE_STATUS GENMASK(14, 13)
213 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
216 #define MT_TX_FREE_RATE GENMASK(13, 0)
236 #define MT_TXD_LEN_MASK GENMASK(11, 0)