55 		mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);  in mt76x2_phy_set_txpower_regs()
56 		mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);  in mt76x2_phy_set_txpower_regs()
59 			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);  in mt76x2_phy_set_txpower_regs()
60 			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);  in mt76x2_phy_set_txpower_regs()
62 			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);  in mt76x2_phy_set_txpower_regs()
63 			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);  in mt76x2_phy_set_txpower_regs()
70 			mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);  in mt76x2_phy_set_txpower_regs()
71 			mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);  in mt76x2_phy_set_txpower_regs()
73 			mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);  in mt76x2_phy_set_txpower_regs()
74 			mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);  in mt76x2_phy_set_txpower_regs()
82 		mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);  in mt76x2_phy_set_txpower_regs()
83 		mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);  in mt76x2_phy_set_txpower_regs()
86 	mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);  in mt76x2_phy_set_txpower_regs()
87 	mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);  in mt76x2_phy_set_txpower_regs()
88 	mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);  in mt76x2_phy_set_txpower_regs()
89 	mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);  in mt76x2_phy_set_txpower_regs()
99 		mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);  in mt76x2_phy_set_txpower_regs()
100 		mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);  in mt76x2_phy_set_txpower_regs()
101 		mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);  in mt76x2_phy_set_txpower_regs()
106 			mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);  in mt76x2_phy_set_txpower_regs()
107 			mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);  in mt76x2_phy_set_txpower_regs()
108 			mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);  in mt76x2_phy_set_txpower_regs()
110 			mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);  in mt76x2_phy_set_txpower_regs()
111 			mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);  in mt76x2_phy_set_txpower_regs()
112 			mt76_wr(dev, MT_TX_ALC_CFG_4, 0);  in mt76x2_phy_set_txpower_regs()
196 	mt76_wr(dev, MT_TX_SW_CFG0, cfg0);  in mt76x2_configure_tx_delay()
197 	mt76_wr(dev, MT_TX_SW_CFG1, cfg1);  in mt76x2_configure_tx_delay()
265 	mt76_wr(dev, MT_BBP(AGC, 8),  in mt76x2_phy_set_gain_val()
267 	mt76_wr(dev, MT_BBP(AGC, 9),  in mt76x2_phy_set_gain_val()
301 		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);  in mt76x2_phy_update_channel_gain()
307 		mt76_wr(dev, MT_BBP(AGC, 26), val);  in mt76x2_phy_update_channel_gain()
309 		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);  in mt76x2_phy_update_channel_gain()
328 		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);  in mt76x2_phy_update_channel_gain()
329 		mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);  in mt76x2_phy_update_channel_gain()
330 		mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);  in mt76x2_phy_update_channel_gain()
334 		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);  in mt76x2_phy_update_channel_gain()
339 	mt76_wr(dev, MT_BBP(AGC, 35), agc_35);  in mt76x2_phy_update_channel_gain()
340 	mt76_wr(dev, MT_BBP(AGC, 37), agc_37);  in mt76x2_phy_update_channel_gain()