Lines Matching refs:GENMASK
43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
48 #define MT7663_TOP_MISC2_FW_STATE GENMASK(3, 1)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
56 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
60 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
61 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
84 #define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0)
85 #define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
112 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
122 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
127 #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
129 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22)
150 #define MT_MCU_CMD_ERROR_MASK (GENMASK(5, 1) | GENMASK(28, 24))
151 #define MT7663_MCU_CMD_ERROR_MASK GENMASK(5, 2)
168 #define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
179 #define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
181 #define MT_HIF1_MIN_QUOTA GENMASK(11, 0)
185 #define MT_HIF_ALL_EMPTY_MASK GENMASK(17, 16)
187 #define MT_PSE_SRC_CNT GENMASK(27, 16)
191 #define MT_PP_TXDWCNT_TX0_ADD_DW_CNT GENMASK(7, 0)
192 #define MT_PP_TXDWCNT_TX1_ADD_DW_CNT GENMASK(15, 8)
204 #define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
205 #define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
210 #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
211 #define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
216 #define MT_WF_PHY_PD_OFDM_MASK(_phy) ((_phy) ? GENMASK(24, 16) : \
217 GENMASK(28, 20))
229 #define MT_WF_PHY_PD_CCK_MASK(_phy) (_phy) ? GENMASK(31, 24) : \
230 GENMASK(8, 1)
239 #define MT_WF_PHY_RFINTF3_0_ANT GENMASK(7, 4)
255 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
256 #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)
258 #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)
263 #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \
269 #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))
275 #define MT_AGG_ACR_CFEND_RATE GENMASK(15, 4)
276 #define MT_AGG_ACR_BAR_RATE GENMASK(31, 20)
302 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
303 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
306 #define MT_TMAC_TRCR_CCA_SEL GENMASK(31, 30)
307 #define MT_TMAC_TRCR_SEC_CCA_SEL GENMASK(29, 28)
310 #define MT_IFS_EIFS GENMASK(8, 0)
311 #define MT_IFS_RIFS GENMASK(14, 10)
312 #define MT_IFS_SIFS GENMASK(22, 16)
313 #define MT_IFS_SLOT GENMASK(30, 24)
316 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
317 #define MT_TMAC_CTCR0_INS_DDLMT_DENSITY GENMASK(15, 12)
348 #define MT_WF_RMAC_MORE_MUAR_MODE GENMASK(31, 30)
361 #define MT_WF_RMAC_MAR1_ADDR GENMASK(15, 0)
364 #define MT_WF_RMAC_MAR1_IDX GENMASK(29, 24)
365 #define MT_WF_RMAC_MAR1_GROUP GENMASK(31, 30)
375 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
381 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2)
392 #define MT_DMA_RCFR0_RX_DROPPED_UCAST GENMASK(25, 24)
393 #define MT_DMA_RCFR0_RX_DROPPED_MCAST GENMASK(27, 26)
407 #define MT_WTBL_W0_KEY_IDX GENMASK(24, 23)
411 #define MT_WTBL_W2_KEY_TYPE GENMASK(7, 4)
414 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
434 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
435 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
436 #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)
439 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
440 #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)
441 #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)
442 #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)
445 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
446 #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)
447 #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)
449 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
454 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
455 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
456 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
457 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
459 #define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5)
465 #define MT_LPON_TCR_MODE GENMASK(1, 0)
466 #define MT_LPON_TCR_READ GENMASK(1, 0)
482 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
485 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
488 #define MT_MIB_AMPDU_MPDU_COUNT GENMASK(23, 0)
491 #define MT_MIB_AMPDU_ACK_COUNT GENMASK(23, 0)
494 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
497 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
499 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
502 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
503 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
506 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
507 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
522 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
523 #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
526 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
527 #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
533 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
550 #define MT_LED_STATUS_OFF GENMASK(31, 24)
551 #define MT_LED_STATUS_ON GENMASK(23, 16)
552 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
563 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
564 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
565 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
566 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
567 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
585 #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)
586 #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8)
589 #define MT_WL_RX_AGG_TO GENMASK(7, 0)
590 #define MT_WL_RX_AGG_LMT GENMASK(15, 8)
606 #define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8))
607 #define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8))