Lines Matching refs:GENMASK
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
41 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
42 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
43 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
47 #define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)
48 #define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)
69 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
70 #define MT_RXD2_NORMAL_TID GENMASK(11, 8)
71 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
75 #define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)
76 #define MT_RXD3_NORMAL_WOL GENMASK(18, 14)
78 #define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)
82 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
84 #define MT_RXD4_FRAME_CONTROL GENMASK(15, 0)
86 #define MT_RXD6_SEQ_CTRL GENMASK(15, 0)
87 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
89 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
93 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
94 #define MT_RXV1_NUM_RX GENMASK(23, 22)
100 #define MT_RXV1_FRAME_MODE GENMASK(16, 15)
101 #define MT_RXV1_TX_MODE GENMASK(14, 12)
102 #define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)
104 #define MT_RXV1_HT_STBC GENMASK(8, 7)
105 #define MT_RXV1_TX_RATE GENMASK(6, 0)
109 #define MT_RXV2_NSTS GENMASK(29, 27)
110 #define MT_RXV2_GROUP_ID GENMASK(26, 21)
111 #define MT_RXV2_LENGTH GENMASK(20, 0)
113 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
114 #define MT_RXV3_IB_RSSI GENMASK(23, 16)
116 #define MT_RXV4_RCPI3 GENMASK(31, 24)
117 #define MT_RXV4_RCPI2 GENMASK(23, 16)
118 #define MT_RXV4_RCPI1 GENMASK(15, 8)
119 #define MT_RXV4_RCPI0 GENMASK(7, 0)
121 #define MT_RXV5_FOE GENMASK(11, 0)
123 #define MT_RXV6_NF3 GENMASK(31, 24)
124 #define MT_RXV6_NF2 GENMASK(23, 16)
125 #define MT_RXV6_NF1 GENMASK(15, 8)
126 #define MT_RXV6_NF0 GENMASK(7, 0)
175 #define MT_TXD0_Q_IDX GENMASK(30, 26)
178 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
179 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
181 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
182 #define MT_TXD1_PKT_FMT GENMASK(25, 24)
183 #define MT_TXD1_TID GENMASK(23, 21)
186 #define MT_TXD1_HDR_PAD GENMASK(18, 17)
189 #define MT_TXD1_HDR_FORMAT GENMASK(14, 13)
190 #define MT_TXD1_HDR_INFO GENMASK(12, 8)
191 #define MT_TXD1_WLAN_IDX GENMASK(7, 0)
196 #define MT_TXD2_POWER_OFFSET GENMASK(28, 24)
197 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
198 #define MT_TXD2_FRAG GENMASK(15, 14)
207 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
208 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
212 #define MT_TXD3_SEQ GENMASK(27, 16)
213 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
214 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
218 #define MT_TXD4_PN_LOW GENMASK(31, 0)
220 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
226 #define MT_TXD5_PID GENMASK(7, 0)
232 #define MT_TXD6_TX_RATE GENMASK(27, 16)
233 #define MT_TXD6_ANT_ID GENMASK(15, 4)
236 #define MT_TXD6_BW GENMASK(1, 0)
240 #define MT_TXD7_TYPE GENMASK(21, 20)
241 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
242 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
245 #define MT_TXD8_L_TYPE GENMASK(5, 4)
246 #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
249 #define MT_TX_RATE_NSS GENMASK(10, 9)
250 #define MT_TX_RATE_MODE GENMASK(8, 6)
251 #define MT_TX_RATE_IDX GENMASK(5, 0)
259 #define MT_TXD_LEN_MASK GENMASK(11, 0)
303 #define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)
305 #define MT_TXS0_PID GENMASK(31, 24)
314 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
320 #define MT_TXS0_TX_RATE GENMASK(11, 0)
322 #define MT_TXS1_ANT_ID GENMASK(31, 20)
323 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
324 #define MT_TXS1_BW GENMASK(15, 14)
327 #define MT_TXS1_TID GENMASK(11, 9)
330 #define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)
332 #define MT_TXS2_WCID GENMASK(31, 24)
333 #define MT_TXS2_RXV_SEQNO GENMASK(23, 16)
334 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
336 #define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
337 #define MT_TXS3_TX_COUNT GENMASK(28, 24)
338 #define MT_TXS3_F1_TSSI1 GENMASK(23, 12)
339 #define MT_TXS3_F1_TSSI0 GENMASK(11, 0)
340 #define MT_TXS3_F0_SEQNO GENMASK(11, 0)
342 #define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
343 #define MT_TXS4_F1_TSSI3 GENMASK(23, 12)
344 #define MT_TXS4_F1_TSSI2 GENMASK(11, 0)
346 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
347 #define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)
348 #define MT_TXS5_F1_NOISE_1 GENMASK(15, 8)
349 #define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)
351 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)
352 #define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)
353 #define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)
354 #define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)