Lines Matching refs:GENMASK
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
74 #define MT_SCH_4_FORCE_QID GENMASK(4, 0)
101 #define MT_MCU_DEBUG_RESET_QUEUES GENMASK(6, 2)
104 #define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0)
105 #define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16)
108 #define MT_PSE_FRP_P0 GENMASK(2, 0)
109 #define MT_PSE_FRP_P1 GENMASK(5, 3)
110 #define MT_PSE_FRP_P2_RQ0 GENMASK(8, 6)
111 #define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9)
112 #define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12)
115 #define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0)
116 #define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)
119 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0)
120 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)
125 #define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0)
126 #define MT_PSE_RTA_PORT_ID GENMASK(6, 5)
128 #define MT_PSE_RTA_TAG_ID GENMASK(15, 8)
142 #define MT_AGC_41_RSSI_0 GENMASK(23, 16)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
149 #define MT_RXTD_6_CCAED_TH GENMASK(14, 8)
151 #define MT_RXTD_8_LOWER_SIGNAL GENMASK(5, 0)
167 #define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
168 #define MT_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
171 #define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
172 #define MT_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
181 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
182 #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)
184 #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)
185 #define MT_AGG_ARCR_SPE_DIS_TH GENMASK(27, 24)
190 #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \
196 #define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)
212 #define MT_AGG_PCR_RTS_THR GENMASK(19, 0)
213 #define MT_AGG_PCR_RTS_PKT_THR GENMASK(31, 25)
216 #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))
222 #define MT_AGG_CONTROL_CFEND_RATE GENMASK(15, 4)
224 #define MT_AGG_CONTROL_BAR_RATE GENMASK(31, 20)
229 #define MT_AGG_BWCR_BW GENMASK(3, 2)
232 #define MT_AGG_RETRY_CONTROL_RTS_LIMIT GENMASK(11, 7)
233 #define MT_AGG_RETRY_CONTROL_BAR_LIMIT GENMASK(15, 12)
239 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 0)
246 #define MT_DMA_FQCR0_TARGET_WCID GENMASK(7, 0)
247 #define MT_DMA_FQCR0_TARGET_BSS GENMASK(13, 8)
248 #define MT_DMA_FQCR0_TARGET_QID GENMASK(20, 16)
249 #define MT_DMA_FQCR0_DEST_PORT_ID GENMASK(23, 22)
250 #define MT_DMA_FQCR0_DEST_QUEUE_ID GENMASK(28, 24)
260 #define MT_DMA_TCFR_TXS_AGGR_TIMEOUT GENMASK(27, 16)
262 #define MT_DMA_TCFR_TXS_AGGR_COUNT GENMASK(12, 8)
263 #define MT_DMA_TCFR_TXS_BIT_MAP GENMASK(6, 0)
271 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
277 #define MT_WMM_CWMAX_MASK GENMASK(15, 0)
280 #define MT_WMM_CWMIN_MASK GENMASK(7, 0)
290 #define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0)
336 #define MT_WF_ARB_CAB_COUNT_MASK GENMASK(3, 0)
345 #define MT_TX_ABORT_WCID GENMASK(15, 8)
351 #define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6)
352 #define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8)
353 #define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)
356 #define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16)
357 #define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18)
374 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
378 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
379 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
382 #define MT_TXREQ_CCA_SRC_SEL GENMASK(31, 30)
385 #define MT_RXREQ_DELAY GENMASK(8, 0)
388 #define MT_IFS_EIFS GENMASK(8, 0)
389 #define MT_IFS_RIFS GENMASK(14, 10)
390 #define MT_IFS_SIFS GENMASK(22, 16)
391 #define MT_IFS_SLOT GENMASK(30, 24)
394 #define MT_TMAC_PCR_RATE GENMASK(8, 0)
396 #define MT_TMAC_PCR_ANT_ID GENMASK(21, 16)
399 #define MT_TMAC_PCR_ANT_PRI GENMASK(26, 24)
400 #define MT_TMAC_PCR_ANT_PRI_SEL GENMASK(27)
434 #define MT_MAC_ADDR1_ADDR GENMASK(15, 0)
439 #define MT_BA_CONTROL_1_ADDR GENMASK(15, 0)
440 #define MT_BA_CONTROL_1_TID GENMASK(19, 16)
448 #define MT_WF_RMACDR_MBSSID_MASK GENMASK(25, 24)
453 #define MT_WF_RMAC_RMCR_SMPS_MODE GENMASK(21, 20)
454 #define MT_WF_RMAC_RMCR_RX_STREAMS GENMASK(24, 22)
466 #define MT_SEC_SCR_MASK_ORDER GENMASK(1, 0)
472 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
487 #define MT_LPON_T0CR_MODE GENMASK(1, 0)
493 #define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29)
496 #define MT_PRE_TBTT_MASK GENMASK(7, 0)
500 #define MT_TBTT_PERIOD GENMASK(15, 0)
501 #define MT_TBTT_DTIM_PERIOD GENMASK(23, 16)
502 #define MT_TBTT_TBTT_WAKE_PERIOD GENMASK(27, 24)
503 #define MT_TBTT_DTIM_WAKE_PERIOD GENMASK(30, 28)
510 #define MT_LPON_SBTOR_TIME_OFFSET GENMASK(19, 0)
529 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
530 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
531 #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)
534 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
535 #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)
536 #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)
537 #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)
540 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
541 #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)
542 #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)
548 #define MT_MIB_CTL_PSCCA_TIME GENMASK(13, 11)
549 #define MT_MIB_CTL_CCA_NAV_TX GENMASK(16, 14)
550 #define MT_MIB_CTL_ED_TIME GENMASK(30, 28)
556 #define MT_MIB_STAT_CCA_MASK GENMASK(23, 0)
559 #define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0)
564 #define MT_MIB_STAT_ED_MASK GENMASK(23, 0)
588 #define MT_LED_STATUS_OFF GENMASK(31, 24)
589 #define MT_LED_STATUS_ON GENMASK(23, 16)
590 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
610 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
611 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
612 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
613 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
614 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
623 #define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0)
637 #define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0)
638 #define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16)
640 #define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23)
649 #define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0)
651 #define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0)
652 #define MT_WTBL1_W2_KEY_TYPE GENMASK(6, 3)
657 #define MT_WTBL1_W2_AMPDU_FACTOR GENMASK(13, 11)
677 #define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0)
678 #define MT_WTBL1_W3_WTBL2_ENTRY_ID GENMASK(15, 11)
679 #define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16)
686 #define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0)
687 #define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11)
688 #define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17)
689 #define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)
691 #define MT_WTBL2_W0_PN_LO GENMASK(31, 0)
693 #define MT_WTBL2_W1_PN_HI GENMASK(15, 0)
694 #define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16)
696 #define MT_WTBL2_W2_TID0_SN GENMASK(11, 0)
697 #define MT_WTBL2_W2_TID1_SN GENMASK(23, 12)
698 #define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24)
700 #define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0)
701 #define MT_WTBL2_W3_TID3_SN GENMASK(15, 4)
702 #define MT_WTBL2_W3_TID4_SN GENMASK(27, 16)
703 #define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28)
705 #define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0)
706 #define MT_WTBL2_W4_TID6_SN GENMASK(19, 8)
707 #define MT_WTBL2_W4_TID7_SN GENMASK(31, 20)
709 #define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0)
712 #define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0)
713 #define MT_WTBL2_W6_TX_COUNT_RATE3 GENMASK(15, 8)
714 #define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16)
715 #define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24)
717 #define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0)
718 #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16)
720 #define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0)
721 #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16)
723 #define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0)
725 #define MT_WTBL2_W9_ANT_PRIORITY GENMASK(8, 6)
726 #define MT_WTBL2_W9_CC_BW_SEL GENMASK(10, 9)
727 #define MT_WTBL2_W9_CHANGE_BW_RATE GENMASK(13, 11)
728 #define MT_WTBL2_W9_BW_CAP GENMASK(15, 14)
733 #define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23)
734 #define MT_WTBL2_W9_MPDU_OK_COUNT GENMASK(28, 26)
735 #define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29)
737 #define MT_WTBL2_W10_RATE1 GENMASK(11, 0)
738 #define MT_WTBL2_W10_RATE2 GENMASK(23, 12)
739 #define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24)
741 #define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0)
742 #define MT_WTBL2_W11_RATE4 GENMASK(15, 4)
743 #define MT_WTBL2_W11_RATE5 GENMASK(27, 16)
744 #define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28)
746 #define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0)
747 #define MT_WTBL2_W12_RATE7 GENMASK(19, 8)
748 #define MT_WTBL2_W12_RATE8 GENMASK(31, 20)
750 #define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0)
751 #define MT_WTBL2_W13_AVG_RCPI1 GENMASK(15, 8)
754 #define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0)
755 #define MT_WTBL2_W14_CC_NOISE_2S GENMASK(13, 7)
756 #define MT_WTBL2_W14_CC_NOISE_3S GENMASK(20, 14)
757 #define MT_WTBL2_W14_CHAN_EST_RMS GENMASK(24, 21)
759 #define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26)
761 #define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(2, 0)
763 #define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24)