135 		iwl_set_bit(trans, CSR_GP_CNTRL,  in iwl_trans_pcie_sw_reset()
138 		iwl_set_bit(trans, CSR_RESET,  in iwl_trans_pcie_sw_reset()
265 	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);  in iwl_pcie_apm_config()
295 		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,  in iwl_pcie_apm_init()
302 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,  in iwl_pcie_apm_init()
306 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);  in iwl_pcie_apm_init()
312 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_apm_init()
319 		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);  in iwl_pcie_apm_init()
440 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_apm_lp_xtal_enable()
471 		iwl_set_bit(trans, CSR_GP_CNTRL,  in iwl_pcie_apm_stop_master()
480 		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);  in iwl_pcie_apm_stop_master()
507 			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,  in iwl_pcie_apm_stop()
509 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_apm_stop()
568 		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);  in iwl_pcie_nic_init()
582 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_set_hw_ready()
592 		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);  in iwl_pcie_set_hw_ready()
614 	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,  in iwl_pcie_prepare_card_hw()
620 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_prepare_card_hw()
893 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_pcie_apply_destination_ini()
944 			iwl_set_bit(trans, addr, BIT(val));  in iwl_pcie_apply_destination()
1561 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,  in iwl_trans_pcie_d3_suspend()
1588 	iwl_set_bit(trans, CSR_GP_CNTRL,  in iwl_trans_pcie_d3_resume()