440 #define FH_TFDIB_CTRL0_REG(_chnl)  (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))  argument
441 #define FH_TFDIB_CTRL1_REG(_chnl)  (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)  argument
472 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl)	\  argument
473 		(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
474 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl)	\  argument
475 		(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
476 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl)	\  argument
477 		(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
541 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)  argument
547 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \  argument
548 		(FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)