Lines Matching refs:b43_phy_mask
204 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF); in lpphy_baseband_rev0_1_init()
218 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE); in lpphy_baseband_rev0_1_init()
325 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev0_1_init()
327 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF); in lpphy_baseband_rev0_1_init()
328 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF); in lpphy_baseband_rev0_1_init()
414 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); in lpphy_baseband_rev2plus_init()
415 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); in lpphy_baseband_rev2plus_init()
429 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF); in lpphy_baseband_rev2plus_init()
463 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev2plus_init()
465 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40); in lpphy_baseband_rev2plus_init()
672 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD); in lpphy_radio_init()
757 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); in lpphy_disable_crs()
759 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); in lpphy_disable_crs()
763 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF); in lpphy_disable_crs()
765 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF); in lpphy_disable_crs()
769 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F); in lpphy_disable_crs()
771 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF); in lpphy_disable_crs()
775 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF); in lpphy_disable_crs()
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF); in lpphy_disable_crs()
785 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80); in lpphy_restore_crs()
786 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00); in lpphy_restore_crs()
793 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE); in lpphy_disable_rx_gain_override()
794 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF); in lpphy_disable_rx_gain_override()
795 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF); in lpphy_disable_rx_gain_override()
797 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_rx_gain_override()
799 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF); in lpphy_disable_rx_gain_override()
800 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7); in lpphy_disable_rx_gain_override()
803 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF); in lpphy_disable_rx_gain_override()
826 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_tx_gain_override()
828 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F); in lpphy_disable_tx_gain_override()
829 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF); in lpphy_disable_tx_gain_override()
831 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF); in lpphy_disable_tx_gain_override()
967 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD); in lpphy_stop_ddfs()
968 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF); in lpphy_stop_ddfs()
975 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80); in lpphy_run_ddfs()
976 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF); in lpphy_run_ddfs()
982 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB); in lpphy_run_ddfs()
992 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7); in lpphy_rx_iq_est()
995 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF); in lpphy_rx_iq_est()
1036 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_loopback()
1164 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD); in lpphy_set_tx_power_control()
1423 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF); in b43_lpphy_op_software_rfkill()
1425 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF); in b43_lpphy_op_software_rfkill()
1426 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF); in b43_lpphy_op_software_rfkill()
1429 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1431 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF); in b43_lpphy_op_software_rfkill()
1435 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1437 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7); in b43_lpphy_op_software_rfkill()
1439 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7); in b43_lpphy_op_software_rfkill()
1466 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7); in lpphy_set_tssi_mux()
1494 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF); in lpphy_tx_pctl_init_hw()
1497 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE); in lpphy_tx_pctl_init_hw()
1504 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF); in lpphy_tx_pctl_init_hw()
1509 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF); in lpphy_tx_pctl_init_hw()
1516 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1529 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1708 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF); in lpphy_calc_rx_iq_comp()
1807 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000); in lpphy_stop_tx_tone()
1904 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1905 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_rx_iq_cal()
1917 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC); in lpphy_rx_iq_cal()
1918 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7); in lpphy_rx_iq_cal()
1919 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF); in lpphy_rx_iq_cal()
1927 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1928 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF); in lpphy_rx_iq_cal()
2664 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8); in b43_lpphy_op_switch_analog()