208 	struct base_eep_header *pBase = &eep->baseEepHeader;  in ath9k_hw_def_dump_eeprom()  local
209 	u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber);  in ath9k_hw_def_dump_eeprom()
225 	PR_EEP("Checksum", le16_to_cpu(pBase->checksum));  in ath9k_hw_def_dump_eeprom()
226 	PR_EEP("Length", le16_to_cpu(pBase->length));  in ath9k_hw_def_dump_eeprom()
227 	PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));  in ath9k_hw_def_dump_eeprom()
228 	PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));  in ath9k_hw_def_dump_eeprom()
229 	PR_EEP("TX Mask", pBase->txMask);  in ath9k_hw_def_dump_eeprom()
230 	PR_EEP("RX Mask", pBase->rxMask);  in ath9k_hw_def_dump_eeprom()
231 	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));  in ath9k_hw_def_dump_eeprom()
232 	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));  in ath9k_hw_def_dump_eeprom()
233 	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
235 	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
237 	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
239 	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
241 	PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));  in ath9k_hw_def_dump_eeprom()
245 	PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);  in ath9k_hw_def_dump_eeprom()
248 			 pBase->macAddr);  in ath9k_hw_def_dump_eeprom()
338 	struct base_eep_header *pBase = &eep->baseEepHeader;  in ath9k_hw_def_get_eeprom()  local
347 		return get_unaligned_be16(pBase->macAddr);  in ath9k_hw_def_get_eeprom()
349 		return get_unaligned_be16(pBase->macAddr + 2);  in ath9k_hw_def_get_eeprom()
351 		return get_unaligned_be16(pBase->macAddr + 4);  in ath9k_hw_def_get_eeprom()
353 		return le16_to_cpu(pBase->regDmn[0]);  in ath9k_hw_def_get_eeprom()
355 		return le16_to_cpu(pBase->deviceCap);  in ath9k_hw_def_get_eeprom()
357 		return pBase->opCapFlags;  in ath9k_hw_def_get_eeprom()
359 		return le16_to_cpu(pBase->rfSilent);  in ath9k_hw_def_get_eeprom()
369 		return pBase->txMask;  in ath9k_hw_def_get_eeprom()
371 		return pBase->rxMask;  in ath9k_hw_def_get_eeprom()
373 		return pBase->fastClk5g;  in ath9k_hw_def_get_eeprom()
375 		return pBase->rxGainType;  in ath9k_hw_def_get_eeprom()
377 		return pBase->txGainType;  in ath9k_hw_def_get_eeprom()
380 			return pBase->openLoopPwrCntl ? true : false;  in ath9k_hw_def_get_eeprom()
385 			return pBase->rcChainMask;  in ath9k_hw_def_get_eeprom()
390 			return pBase->dacHiPwrMode_5G;  in ath9k_hw_def_get_eeprom()
395 			return pBase->frac_n_5g;  in ath9k_hw_def_get_eeprom()
400 			return pBase->pwr_table_offset;  in ath9k_hw_def_get_eeprom()