Lines Matching refs:GENMASK
10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
476 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
477 #define HAL_TLV_USR_ID GENMASK(31, 26)
486 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
487 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
500 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
576 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)
577 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17)
678 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
680 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9)
681 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11)
682 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16)
685 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1)
686 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5)
688 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20)
689 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
786 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
787 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)
788 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)
791 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
792 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)
862 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
863 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)
864 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7)
866 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12)
869 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
870 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20)
871 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)
881 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
888 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
929 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
931 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)
940 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
943 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)
957 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2)
958 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4)
961 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12)
962 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14)
963 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16)
965 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0)
972 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23)
974 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0)
978 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22)
979 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26)
981 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0)
982 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6)
983 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26)
984 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30)
986 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20)
987 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28)
1208 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0)
1209 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8)
1214 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20)
1215 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28)
1256 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0)
1258 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5)
1259 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8)
1261 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0)
1263 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20)
1264 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
1299 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1304 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)
1306 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
1308 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)
1396 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1397 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)
1449 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)
1451 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
1452 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)
1528 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)
1529 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3)
1532 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9)
1533 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11)
1535 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16)
1636 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1637 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)
1638 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)
1639 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
1640 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)
1641 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1642 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1643 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1644 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1647 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1648 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
1650 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1656 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
1658 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0)
1659 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16)
1660 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20)
1661 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28)
1663 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9)
1664 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13)
1890 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
1891 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
1892 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)
1907 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
1941 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
1944 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)
1947 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)
1952 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11)
1957 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23)
1961 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)
1962 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13)
1967 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
1970 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)
1971 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)
1972 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)
1974 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
1975 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)
1977 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
1978 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)
1979 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)
2069 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
2094 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
2096 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)
2099 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)
2110 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
2111 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8)
2113 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11)
2128 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)
2143 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
2144 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)
2145 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)
2170 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
2171 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12)
2173 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
2174 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)
2176 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)
2177 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)
2178 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)
2180 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
2181 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)
2183 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
2184 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12)
2185 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16)
2187 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)
2278 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)
2281 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)
2282 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
2312 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)
2314 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)
2315 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)
2316 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)
2317 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)
2414 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
2415 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)
2454 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
2455 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
2456 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
2457 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
2458 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)