152 			  ar->hw_ce_regs->dst_wr_index_addr, n);  in ath10k_ce_dest_ring_write_index_set()
159 				ar->hw_ce_regs->dst_wr_index_addr);  in ath10k_ce_dest_ring_write_index_get()
167 			  ar->hw_ce_regs->sr_wr_index_addr, n);  in ath10k_ce_src_ring_write_index_set()
174 				ar->hw_ce_regs->sr_wr_index_addr);  in ath10k_ce_src_ring_write_index_get()
198 					 ar->hw_ce_regs->current_srri_addr);  in ath10k_ce_src_ring_read_index_get()
229 			  ar->hw_ce_regs->sr_base_addr_lo, addr_lo);  in ath10k_ce_src_ring_base_addr_set()
244 			  ar->hw_ce_regs->sr_base_addr_hi, addr_hi);  in ath10k_ce_set_src_ring_base_addr_hi()
252 			  ar->hw_ce_regs->sr_size_addr, n);  in ath10k_ce_src_ring_size_set()
259 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_src_ring_dmax_set()
273 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_src_ring_byte_swap_set()
287 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_dest_ring_byte_swap_set()
319 					 ar->hw_ce_regs->current_drri_addr);  in ath10k_ce_dest_ring_read_index_get()
334 			  ar->hw_ce_regs->dr_base_addr_lo, addr_lo);  in ath10k_ce_dest_ring_base_addr_set()
350 				     ar->hw_ce_regs->dr_base_addr_hi);  in ath10k_ce_set_dest_ring_base_addr_hi()
354 			  ar->hw_ce_regs->dr_base_addr_hi, reg_value);  in ath10k_ce_set_dest_ring_base_addr_hi()
362 			  ar->hw_ce_regs->dr_size_addr, n);  in ath10k_ce_dest_ring_size_set()
369 	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;  in ath10k_ce_src_ring_highmark_set()
381 	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;  in ath10k_ce_src_ring_lowmark_set()
393 	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;  in ath10k_ce_dest_ring_highmark_set()
405 	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;  in ath10k_ce_dest_ring_lowmark_set()
416 	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;  in ath10k_ce_copy_complete_inter_enable()
419 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_copy_complete_inter_enable()
421 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_copy_complete_inter_enable()
428 	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;  in ath10k_ce_copy_complete_intr_disable()
431 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_copy_complete_intr_disable()
433 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_copy_complete_intr_disable()
440 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_watermark_intr_disable()
443 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_watermark_intr_disable()
445 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_watermark_intr_disable()
452 	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;  in ath10k_ce_error_intr_enable()
455 					    ar->hw_ce_regs->misc_ie_addr);  in ath10k_ce_error_intr_enable()
458 			  ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,  in ath10k_ce_error_intr_enable()
465 	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;  in ath10k_ce_error_intr_disable()
468 			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);  in ath10k_ce_error_intr_disable()
471 			  ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,  in ath10k_ce_error_intr_disable()
479 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_engine_int_status_clear()
1299 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_per_engine_service()
2011 	ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_low,  in ath10k_ce_alloc_rri()
2013 	ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_high,  in ath10k_ce_alloc_rri()
2018 		ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr;  in ath10k_ce_alloc_rri()
2021 		value |= ar->hw_ce_regs->upd->mask;  in ath10k_ce_alloc_rri()