692 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)  in phy_base_write()  function
719 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_read()
729 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_read()
739 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_read()
761 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_read()
772 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_write()
782 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_write()
786 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);  in vsc85xx_csr_write()
789 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));  in vsc85xx_csr_write()
798 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_write()
814 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_write()
823 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);  in vsc8584_csr_write()
824 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));  in vsc8584_csr_write()
825 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));  in vsc8584_csr_write()
834 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_cmd()
837 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);  in vsc8584_cmd()
846 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_cmd()
863 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_deassert_reset()
875 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_micro_deassert_reset()
881 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);  in vsc8584_micro_deassert_reset()
883 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);  in vsc8584_micro_deassert_reset()
885 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_deassert_reset()
900 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_assert_reset()
905 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
907 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
908 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
912 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
914 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);  in vsc8584_micro_assert_reset()
918 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);  in vsc8584_micro_assert_reset()
920 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |  in vsc8584_micro_assert_reset()
926 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
928 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_assert_reset()
939 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
941 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);  in vsc8584_get_fw_crc()
942 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);  in vsc8584_get_fw_crc()
949 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
954 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_get_fw_crc()
972 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_patch_fw()
978 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |  in vsc8584_patch_fw()
981 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |  in vsc8584_patch_fw()
983 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);  in vsc8584_patch_fw()
986 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |  in vsc8584_patch_fw()
990 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_patch_fw()
992 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_patch_fw()
1003 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_is_serdes_init()
1033 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_is_serdes_init()
1112 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1117 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1119 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8574_config_pre_init()
1126 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);  in vsc8574_config_pre_init()
1128 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1130 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);  in vsc8574_config_pre_init()
1131 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);  in vsc8574_config_pre_init()
1132 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);  in vsc8574_config_pre_init()
1133 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);  in vsc8574_config_pre_init()
1137 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1139 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1144 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8574_config_pre_init()
1146 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8574_config_pre_init()
1148 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1153 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1157 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1159 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1164 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1203 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1206 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);  in vsc8574_config_pre_init()
1207 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);  in vsc8574_config_pre_init()
1208 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,  in vsc8574_config_pre_init()
1227 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1234 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1371 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1376 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1378 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8584_config_pre_init()
1382 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);  in vsc8584_config_pre_init()
1389 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);  in vsc8584_config_pre_init()
1391 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);  in vsc8584_config_pre_init()
1393 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1395 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);  in vsc8584_config_pre_init()
1399 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1401 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1403 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));  in vsc8584_config_pre_init()
1408 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);  in vsc8584_config_pre_init()
1410 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));  in vsc8584_config_pre_init()
1415 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8584_config_pre_init()
1417 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8584_config_pre_init()
1419 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1424 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1428 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1430 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1435 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1476 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);  in vsc8584_config_pre_init()
1478 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);  in vsc8584_config_pre_init()
1483 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);  in vsc8584_config_pre_init()
1489 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_config_pre_init()
1496 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1564 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_host_serdes()
1580 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8584_config_host_serdes()
1584 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_host_serdes()
1629 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_host_serdes()
1647 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8574_config_host_serdes()
1651 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_host_serdes()
1902 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_host_serdes()
1910 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8514_config_host_serdes()
1914 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_host_serdes()
1944 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);  in vsc8514_config_host_serdes()
1990 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
1995 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
1997 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
2001 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
2003 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8514_config_pre_init()
2008 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
2012 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
2014 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
2018 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
2029 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_pre_init()
2033 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);  in vsc8514_config_pre_init()
2038 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);  in vsc8514_config_pre_init()
2043 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8514_config_pre_init()