Lines Matching refs:value
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
42 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
53 u32 value; in dwxgmac2_dma_init_rx_chan() local
55 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
56 value &= ~XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
57 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
58 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
69 u32 value; in dwxgmac2_dma_init_tx_chan() local
71 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
72 value &= ~XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
73 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
74 value |= XGMAC_OSP; in dwxgmac2_dma_init_tx_chan()
75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
87 value |= XGMAC_EN_LPI; in dwxgmac2_dma_axi()
89 value |= XGMAC_LPI_XIT_PKT; in dwxgmac2_dma_axi()
91 value &= ~XGMAC_WR_OSR_LMT; in dwxgmac2_dma_axi()
92 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
95 value &= ~XGMAC_RD_OSR_LMT; in dwxgmac2_dma_axi()
96 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
100 value |= XGMAC_UNDEF; in dwxgmac2_dma_axi()
102 value &= ~XGMAC_BLEN; in dwxgmac2_dma_axi()
106 value |= XGMAC_BLEN256; in dwxgmac2_dma_axi()
109 value |= XGMAC_BLEN128; in dwxgmac2_dma_axi()
112 value |= XGMAC_BLEN64; in dwxgmac2_dma_axi()
115 value |= XGMAC_BLEN32; in dwxgmac2_dma_axi()
118 value |= XGMAC_BLEN16; in dwxgmac2_dma_axi()
121 value |= XGMAC_BLEN8; in dwxgmac2_dma_axi()
124 value |= XGMAC_BLEN4; in dwxgmac2_dma_axi()
129 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
149 value |= XGMAC_RSF; in dwxgmac2_dma_rx_mode()
151 value &= ~XGMAC_RSF; in dwxgmac2_dma_rx_mode()
152 value &= ~XGMAC_RTC; in dwxgmac2_dma_rx_mode()
155 value |= 0x0 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
157 value |= 0x2 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
159 value |= 0x3 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
162 value &= ~XGMAC_RQS; in dwxgmac2_dma_rx_mode()
163 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; in dwxgmac2_dma_rx_mode()
169 value |= XGMAC_EHFC; in dwxgmac2_dma_rx_mode()
201 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
204 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
205 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
215 value |= XGMAC_TSF; in dwxgmac2_dma_tx_mode()
217 value &= ~XGMAC_TSF; in dwxgmac2_dma_tx_mode()
218 value &= ~XGMAC_TTC; in dwxgmac2_dma_tx_mode()
221 value |= 0x0 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
223 value |= 0x2 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
225 value |= 0x3 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
227 value |= 0x4 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
229 value |= 0x5 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
231 value |= 0x6 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
233 value |= 0x7 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
237 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; in dwxgmac2_dma_tx_mode()
239 value &= ~XGMAC_TXQEN; in dwxgmac2_dma_tx_mode()
241 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
243 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
245 value &= ~XGMAC_TQS; in dwxgmac2_dma_tx_mode()
246 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; in dwxgmac2_dma_tx_mode()
248 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
254 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq() local
257 value |= XGMAC_DMA_INT_DEFAULT_RX; in dwxgmac2_enable_dma_irq()
259 value |= XGMAC_DMA_INT_DEFAULT_TX; in dwxgmac2_enable_dma_irq()
261 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq()
267 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq() local
270 value &= ~XGMAC_DMA_INT_DEFAULT_RX; in dwxgmac2_disable_dma_irq()
272 value &= ~XGMAC_DMA_INT_DEFAULT_TX; in dwxgmac2_disable_dma_irq()
274 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq()
279 u32 value; in dwxgmac2_dma_start_tx() local
281 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
282 value |= XGMAC_TXST; in dwxgmac2_dma_start_tx()
283 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
285 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
286 value |= XGMAC_CONFIG_TE; in dwxgmac2_dma_start_tx()
287 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
292 u32 value; in dwxgmac2_dma_stop_tx() local
294 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
295 value &= ~XGMAC_TXST; in dwxgmac2_dma_stop_tx()
296 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
298 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
299 value &= ~XGMAC_CONFIG_TE; in dwxgmac2_dma_stop_tx()
300 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
305 u32 value; in dwxgmac2_dma_start_rx() local
307 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
308 value |= XGMAC_RXST; in dwxgmac2_dma_start_rx()
309 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
311 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
312 value |= XGMAC_CONFIG_RE; in dwxgmac2_dma_start_rx()
313 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
318 u32 value; in dwxgmac2_dma_stop_rx() local
320 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
321 value &= ~XGMAC_RXST; in dwxgmac2_dma_stop_rx()
322 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
479 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso() local
482 value |= XGMAC_TSE; in dwxgmac2_enable_tso()
484 value &= ~XGMAC_TSE; in dwxgmac2_enable_tso()
486 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
491 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode() local
494 value &= ~XGMAC_TXQEN; in dwxgmac2_qmode()
496 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
499 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
503 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
508 u32 value; in dwxgmac2_set_bfsize() local
510 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
511 value &= ~XGMAC_RBSZ; in dwxgmac2_set_bfsize()
512 value |= bfsize << XGMAC_RBSZ_SHIFT; in dwxgmac2_set_bfsize()
513 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
518 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph() local
520 value &= ~XGMAC_CONFIG_HDSMS; in dwxgmac2_enable_sph()
521 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ in dwxgmac2_enable_sph()
522 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
524 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
526 value |= XGMAC_SPH; in dwxgmac2_enable_sph()
528 value &= ~XGMAC_SPH; in dwxgmac2_enable_sph()
529 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
534 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs() local
537 value |= XGMAC_EDSE; in dwxgmac2_enable_tbs()
539 value &= ~XGMAC_EDSE; in dwxgmac2_enable_tbs()
541 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()
543 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE; in dwxgmac2_enable_tbs()
544 if (en && !value) in dwxgmac2_enable_tbs()