3307 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3342 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_force_linkspeed()
3344 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_force_linkspeed()
3346 		txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_force_linkspeed()
3348 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3351 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_force_linkspeed()
3355 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_force_linkspeed()
3357 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_force_linkspeed()
3359 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3391 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3523 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_update_linkspeed()
3527 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;  in nv_update_linkspeed()
3529 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;  in nv_update_linkspeed()
3531 				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_update_linkspeed()
3536 			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;  in nv_update_linkspeed()
3538 			txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_update_linkspeed()
3540 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3543 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_update_linkspeed()
3546 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_update_linkspeed()
3548 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_update_linkspeed()
3550 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
5716 	u32 powerstate, txreg;  in nv_probe()  local
5891 	txreg = readl(base + NvRegTransmitPoll);  in nv_probe()
5900 	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {  in nv_probe()
5924 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()