1263 	u32 phy_reserved;  in init_realtek_8201()  local
1266 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201()
1268 		phy_reserved |= PHY_REALTEK_INIT7;  in init_realtek_8201()
1270 			   PHY_REALTEK_INIT_REG6, phy_reserved))  in init_realtek_8201()
1279 	u32 phy_reserved;  in init_realtek_8201_cross()  local
1285 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201_cross()
1287 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in init_realtek_8201_cross()
1288 		phy_reserved |= PHY_REALTEK_INIT3;  in init_realtek_8201_cross()
1290 			   PHY_REALTEK_INIT_REG2, phy_reserved))  in init_realtek_8201_cross()
1303 	u32 phy_reserved;  in init_cicada()  local
1306 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1307 		phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);  in init_cicada()
1308 		phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);  in init_cicada()
1309 		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))  in init_cicada()
1311 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1312 		phy_reserved |= PHY_CICADA_INIT5;  in init_cicada()
1313 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))  in init_cicada()
1316 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1317 	phy_reserved |= PHY_CICADA_INIT6;  in init_cicada()
1318 	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))  in init_cicada()
1326 	u32 phy_reserved;  in init_vitesse()  local
1334 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1336 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1338 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1340 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1341 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1342 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1350 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1352 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1353 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1354 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1356 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1358 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1366 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1368 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1370 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1372 	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;  in init_vitesse()
1373 	phy_reserved |= PHY_VITESSE_INIT8;  in init_vitesse()
1374 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
6162 	u16 phy_reserved, mii_control;  in nv_restore_phy()  local
6168 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6169 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in nv_restore_phy()
6170 		phy_reserved |= PHY_REALTEK_INIT8;  in nv_restore_phy()
6171 		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);  in nv_restore_phy()