1137 #define MII_READ	(-1)  macro
1157 	if (value != MII_READ) {  in mii_rw()
1166 	} else if (value != MII_READ) {  in mii_rw()
1194 		miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_reset()
1241 	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);  in init_realtek_8211c()
1248 	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);  in init_realtek_8211c()
1267 				      PHY_REALTEK_INIT_REG6, MII_READ);  in init_realtek_8201()
1286 				      PHY_REALTEK_INIT_REG2, MII_READ);  in init_realtek_8201_cross()
1306 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1311 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1316 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1335 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1339 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1351 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1357 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1367 			      PHY_VITESSE_INIT_REG4, MII_READ);  in init_vitesse()
1371 			      PHY_VITESSE_INIT_REG3, MII_READ);  in init_vitesse()
1395 		reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in phy_init()
1428 	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in phy_init()
1442 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in phy_init()
1446 					  MII_CTRL1000, MII_READ);  in phy_init()
1461 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_init()
1521 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in phy_init()
3314 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_force_linkspeed()
3398 	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_update_linkspeed()
3411 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_update_linkspeed()
3412 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_update_linkspeed()
3447 	adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_update_linkspeed()
3448 	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);  in nv_update_linkspeed()
3452 		control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_update_linkspeed()
3453 		status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);  in nv_update_linkspeed()
3520 	phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */  in nv_update_linkspeed()
4378 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_get_link_ksettings()
4388 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_get_link_ksettings()
4483 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_link_ksettings()
4500 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_set_link_ksettings()
4509 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_link_ksettings()
4527 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_link_ksettings()
4550 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);  in nv_set_link_ksettings()
4555 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_link_ksettings()
4629 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_nway_reset()
4841 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);  in nv_set_pauseparam()
4851 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_pauseparam()
4882 	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_set_loopback()
5036 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_link_test()
5037 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_link_test()
5467 	       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);  in nv_open()
5666 		       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);  in nv_close()
6053 		id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);  in nv_probe()
6058 		id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);  in nv_probe()
6074 			np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;  in nv_probe()
6088 		u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);  in nv_probe()
6168 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6175 		mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);  in nv_restore_phy()