55 	enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);  in enetc_set_vlan_promisc()
77 	enetc_port_wr(hw, ENETC_PSIVLANR(si), val);  in enetc_set_isol_vlan()
127 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);  in enetc_clear_mac_ht_flt()
128 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);  in enetc_clear_mac_ht_flt()
130 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);  in enetc_clear_mac_ht_flt()
131 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);  in enetc_clear_mac_ht_flt()
141 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),  in enetc_set_mac_ht_flt()
143 		enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),  in enetc_set_mac_ht_flt()
146 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),  in enetc_set_mac_ht_flt()
148 		enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),  in enetc_set_mac_ht_flt()
255 	enetc_port_wr(hw, ENETC_PSIPMR, psipmr);  in enetc_pf_set_rx_mode()
261 	enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));  in enetc_set_vlan_ht_filter()
262 	enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));  in enetc_set_vlan_ht_filter()
330 		enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);  in enetc_set_loopback()
338 		enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);  in enetc_set_loopback()
339 		enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);  in enetc_set_loopback()
392 	enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);  in enetc_pf_set_vf_spoofchk()
460 		enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);  in enetc_port_assign_rfs_entries()
461 	enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),  in enetc_port_assign_rfs_entries()
465 	enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);  in enetc_port_assign_rfs_entries()
494 	enetc_port_wr(hw, ENETC_PSICFGR0(0), val);  in enetc_port_si_configure()
510 		enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);  in enetc_port_si_configure()
514 	enetc_port_wr(hw, ENETC_PVCLCTR, val);  in enetc_port_si_configure()
516 	enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);  in enetc_port_si_configure()
523 	enetc_port_wr(hw, ENETC_PM0_MAXFRM,  in enetc_configure_port_mac()
527 		enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);  in enetc_configure_port_mac()
529 	enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |  in enetc_configure_port_mac()
532 	enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |  in enetc_configure_port_mac()
539 	enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);  in enetc_configure_port_mac()
550 		enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);  in enetc_mac_config()
555 		enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);  in enetc_mac_config()
566 	enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);  in enetc_mac_enable()
567 	enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);  in enetc_mac_enable()
576 	enetc_port_wr(hw, ENETC_PFPMR,  in enetc_configure_port_pmac()
580 	enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);  in enetc_configure_port_pmac()
605 	enetc_port_wr(hw, ENETC_PSIPMR, 0);  in enetc_configure_port()
608 	enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);  in enetc_configure_port()
976 	enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);  in enetc_force_rgmii_mac()
1035 	enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);  in enetc_pl_mac_link_up()
1036 	enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);  in enetc_pl_mac_link_up()
1037 	enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);  in enetc_pl_mac_link_up()
1038 	enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);  in enetc_pl_mac_link_up()
1039 	enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);  in enetc_pl_mac_link_up()
1040 	enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);  in enetc_pl_mac_link_up()
1049 	enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);  in enetc_pl_mac_link_up()
1050 	enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);  in enetc_pl_mac_link_up()