102 	REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);  in bnx2x_vf_igu_ack_sb()
107 	REG_WR(bp, igu_addr_ctl, ctl);  in bnx2x_vf_igu_ack_sb()
681 	REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);  in bnx2x_vf_enable_internal()
687 	REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
688 	REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
689 	REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
690 	REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
712 	REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));  in bnx2x_vf_pglue_clear_err()
723 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);  in bnx2x_vf_igu_reset()
724 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);  in bnx2x_vf_igu_reset()
725 	REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);  in bnx2x_vf_igu_reset()
726 	REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);  in bnx2x_vf_igu_reset()
727 	REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);  in bnx2x_vf_igu_reset()
728 	REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);  in bnx2x_vf_igu_reset()
734 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);  in bnx2x_vf_igu_reset()
747 		REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);  in bnx2x_vf_igu_reset()
792 	REG_WR(bp, PBF_REG_DISABLE_VF, 0);  in bnx2x_vf_enable_traffic()
996 	REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);  in bnx2x_iov_init_dq()
997 	REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));  in bnx2x_iov_init_dq()
1002 	REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);  in bnx2x_iov_init_dq()
1005 	REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);  in bnx2x_iov_init_dq()
1010 	REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);  in bnx2x_iov_init_dq()
1016 	REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);  in bnx2x_iov_init_dq()
1017 	REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);  in bnx2x_iov_init_dq()
1018 	REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);  in bnx2x_iov_init_dq()
1019 	REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);  in bnx2x_iov_init_dq()
1024 	REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);  in bnx2x_iov_init_dq()
1030 		REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);  in bnx2x_iov_init_dmae()
1957 	REG_WR(bp, reg, val);  in bnx2x_vf_qtbl_set_q()
1978 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);  in bnx2x_vf_igu_disable()
2115 	REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);  in bnx2x_vf_init()
2477 			REG_WR(bp, address, igu_entry);  in bnx2x_enable_sriov()
2505 		REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,  in bnx2x_enable_sriov()