323 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,  in m_can_write()  function
387 		m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);  in m_can_config_endisable()
390 		m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);  in m_can_config_endisable()
392 		m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));  in m_can_config_endisable()
412 	m_can_write(cdev, M_CAN_ILE, ILE_EINT0);  in m_can_enable_all_interrupts()
417 	m_can_write(cdev, M_CAN_ILE, 0x0);  in m_can_disable_all_interrupts()
530 	m_can_write(cdev, M_CAN_RXF0A, fgi);  in m_can_read_fifo()
919 			m_can_write(cdev, M_CAN_IR, IR_MRAF);  in m_can_rx_handler()
1036 		m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,  in m_can_echo_tx_event()
1060 		m_can_write(cdev, M_CAN_IR, ir);  in m_can_isr()
1175 	m_can_write(cdev, M_CAN_NBTP, reg_btp);  in m_can_set_bittiming()
1210 			m_can_write(cdev, M_CAN_TDCR,  in m_can_set_bittiming()
1219 		m_can_write(cdev, M_CAN_DBTP, reg_btp);  in m_can_set_bittiming()
1243 	m_can_write(cdev, M_CAN_RXESC,  in m_can_chip_config()
1249 	m_can_write(cdev, M_CAN_GFC, 0x0);  in m_can_chip_config()
1253 		m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |  in m_can_chip_config()
1257 		m_can_write(cdev, M_CAN_TXBC,  in m_can_chip_config()
1264 	m_can_write(cdev, M_CAN_TXESC,  in m_can_chip_config()
1269 		m_can_write(cdev, M_CAN_TXEFC,  in m_can_chip_config()
1274 		m_can_write(cdev, M_CAN_TXEFC,  in m_can_chip_config()
1281 	m_can_write(cdev, M_CAN_RXF0C,  in m_can_chip_config()
1285 	m_can_write(cdev, M_CAN_RXF1C,  in m_can_chip_config()
1330 	m_can_write(cdev, M_CAN_CCCR, cccr);  in m_can_chip_config()
1331 	m_can_write(cdev, M_CAN_TEST, test);  in m_can_chip_config()
1334 	m_can_write(cdev, M_CAN_IR, IR_ALL_INT);  in m_can_chip_config()
1337 			m_can_write(cdev, M_CAN_IE, IR_ALL_INT &  in m_can_chip_config()
1340 			m_can_write(cdev, M_CAN_IE, IR_ALL_INT &  in m_can_chip_config()
1343 		m_can_write(cdev, M_CAN_IE, IR_ALL_INT);  in m_can_chip_config()
1346 	m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);  in m_can_chip_config()
1354 	m_can_write(cdev, M_CAN_TSCC,  in m_can_chip_config()
1433 	m_can_write(cdev, M_CAN_CCCR, cccr_reg);  in m_can_niso_supported()
1447 	m_can_write(cdev, M_CAN_CCCR, cccr_reg);  in m_can_niso_supported()
1633 			m_can_write(cdev, M_CAN_CCCR, cccr);  in m_can_tx_handler()
1635 		m_can_write(cdev, M_CAN_TXBTIE, 0x1);  in m_can_tx_handler()
1639 		m_can_write(cdev, M_CAN_TXBAR, 0x1);  in m_can_tx_handler()
1695 		m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));  in m_can_tx_handler()