1213 		u32 reg_fdcbt, reg_ctrl2;  in flexcan_set_bittiming_cbt()  local
1249 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_set_bittiming_cbt()
1250 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1252 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1254 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);  in flexcan_set_bittiming_cbt()
1255 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_set_bittiming_cbt()
1318 	u32 reg_ctrl2;  in flexcan_ram_init()  local
1328 	reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_ram_init()
1329 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1330 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1337 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1338 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1420 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;  in flexcan_chip_start()  local
1528 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1529 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;  in flexcan_chip_start()
1530 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1609 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1610 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1611 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1629 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1630 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()