Lines Matching refs:GENMASK

95 #define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
96 #define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
97 #define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
108 #define REG_MODE_RTRTH GENMASK(20, 17)
150 #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
153 #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
156 #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
159 #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
162 #define REG_BTR_PROP GENMASK(6, 0)
163 #define REG_BTR_PH1 GENMASK(12, 7)
164 #define REG_BTR_PH2 GENMASK(18, 13)
165 #define REG_BTR_BRP GENMASK(26, 19)
166 #define REG_BTR_SJW GENMASK(31, 27)
169 #define REG_BTR_FD_PROP_FD GENMASK(5, 0)
170 #define REG_BTR_FD_PH1_FD GENMASK(11, 7)
171 #define REG_BTR_FD_PH2_FD GENMASK(17, 13)
172 #define REG_BTR_FD_BRP_FD GENMASK(26, 19)
173 #define REG_BTR_FD_SJW_FD GENMASK(31, 27)
176 #define REG_EWL_EW_LIMIT GENMASK(7, 0)
177 #define REG_EWL_ERP_LIMIT GENMASK(15, 8)
183 #define REG_REC_REC_VAL GENMASK(8, 0)
184 #define REG_REC_TEC_VAL GENMASK(24, 16)
187 #define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
188 #define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
191 #define REG_CTR_PRES_CTPV GENMASK(8, 0)
198 #define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
201 #define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
204 #define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
207 #define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
210 #define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
213 #define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
216 #define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
219 #define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
244 #define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
245 #define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
248 #define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
249 #define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
255 #define REG_RX_STATUS_RXFRC GENMASK(14, 4)
259 #define REG_RX_DATA_RX_DATA GENMASK(31, 0)
262 #define REG_TX_STATUS_TX1S GENMASK(3, 0)
263 #define REG_TX_STATUS_TX2S GENMASK(7, 4)
264 #define REG_TX_STATUS_TX3S GENMASK(11, 8)
265 #define REG_TX_STATUS_TX4S GENMASK(15, 12)
277 #define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
278 #define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
279 #define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
280 #define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
283 #define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
284 #define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
285 #define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
286 #define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
289 #define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
290 #define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
291 #define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
294 #define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
297 #define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
300 #define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
301 #define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
317 #define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
320 #define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
323 #define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)