167 		out_be32(&lbc->fbar, page_addr >> 6);  in set_addr()
168 		out_be32(&lbc->fpar,  in set_addr()
177 		out_be32(&lbc->fbar, page_addr >> 5);  in set_addr()
178 		out_be32(&lbc->fpar,  in set_addr()
211 	out_be32(&lbc->fmr, priv->fmr | 3);  in fsl_elbc_run_command()
213 		out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);  in fsl_elbc_run_command()
226 	out_be32(&lbc->lsor, priv->bank);  in fsl_elbc_run_command()
265 			out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */  in fsl_elbc_run_command()
282 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
289 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |  in fsl_elbc_do_read()
292 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
299 			out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
301 			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
333 		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */  in fsl_elbc_cmdfunc()
358 		out_be32(&lbc->fbcr, mtd->oobsize - column);  in fsl_elbc_cmdfunc()
371 		out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |  in fsl_elbc_cmdfunc()
374 		out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
379 		out_be32(&lbc->fbcr, 256);  in fsl_elbc_cmdfunc()
399 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
406 		out_be32(&lbc->fcr,  in fsl_elbc_cmdfunc()
411 		out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
443 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
452 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
470 		out_be32(&lbc->fcr, fcr);  in fsl_elbc_cmdfunc()
487 			out_be32(&lbc->fbcr,  in fsl_elbc_cmdfunc()
490 			out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
499 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
502 		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
503 		out_be32(&lbc->fbcr, 1);  in fsl_elbc_cmdfunc()
518 		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);  in fsl_elbc_cmdfunc()
519 		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()