163 	u32 scratch_32;  in o2_pci_set_baseclk()  local
166 			      O2_SD_PLL_SETTING, &scratch_32);  in o2_pci_set_baseclk()
168 	scratch_32 &= 0x0000FFFF;  in o2_pci_set_baseclk()
169 	scratch_32 |= value;  in o2_pci_set_baseclk()
172 			       O2_SD_PLL_SETTING, scratch_32);  in o2_pci_set_baseclk()
242 	u32 scratch_32 = 0;  in sdhci_o2_dll_recovery()  local
257 		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
258 		scratch_32 |= O2_PLL_SOFT_RESET;  in sdhci_o2_dll_recovery()
259 		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
263 					    &scratch_32);  in sdhci_o2_dll_recovery()
265 		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_o2_dll_recovery()
266 		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);  in sdhci_o2_dll_recovery()
414 	u32 scratch_32;  in o2_pci_led_enable()  local
418 				    O2_SD_FUNC_REG0, &scratch_32);  in o2_pci_led_enable()
422 	scratch_32 &= ~O2_SD_FREG0_LEDOFF;  in o2_pci_led_enable()
424 			       O2_SD_FUNC_REG0, scratch_32);  in o2_pci_led_enable()
427 				    O2_SD_TEST_REG, &scratch_32);  in o2_pci_led_enable()
431 	scratch_32 |= O2_SD_LED_ENABLE;  in o2_pci_led_enable()
433 			       O2_SD_TEST_REG, scratch_32);  in o2_pci_led_enable()
438 	u32 scratch_32;  in sdhci_pci_o2_fujin2_pci_init()  local
441 	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
444 	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));  in sdhci_pci_o2_fujin2_pci_init()
445 	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
448 	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
451 	scratch_32 &= ~((1 << 19) | (1 << 11));  in sdhci_pci_o2_fujin2_pci_init()
452 	scratch_32 |= (1 << 10);  in sdhci_pci_o2_fujin2_pci_init()
453 	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
456 	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
459 	scratch_32 |= (1 << 4);  in sdhci_pci_o2_fujin2_pci_init()
460 	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
466 	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
469 	scratch_32 &= ~(3 << 12);  in sdhci_pci_o2_fujin2_pci_init()
470 	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
473 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
476 	scratch_32 &= ~(0x01FE);  in sdhci_pci_o2_fujin2_pci_init()
477 	scratch_32 |= 0x00CC;  in sdhci_pci_o2_fujin2_pci_init()
478 	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
481 				    O2_SD_TUNING_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
484 	scratch_32 &= ~(0x000000FF);  in sdhci_pci_o2_fujin2_pci_init()
485 	scratch_32 |= 0x00000066;  in sdhci_pci_o2_fujin2_pci_init()
486 	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
490 				    O2_SD_UHS2_L1_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
493 	scratch_32 &= ~(0x000000FC);  in sdhci_pci_o2_fujin2_pci_init()
494 	scratch_32 |= 0x00000084;  in sdhci_pci_o2_fujin2_pci_init()
495 	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
498 	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
501 	scratch_32 &= ~((1 << 21) | (1 << 30));  in sdhci_pci_o2_fujin2_pci_init()
503 	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
506 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
509 	scratch_32 &= ~(0xf0000000);  in sdhci_pci_o2_fujin2_pci_init()
510 	scratch_32 |= 0x30000000;  in sdhci_pci_o2_fujin2_pci_init()
511 	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
514 				    O2_SD_MISC_CTRL4, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
517 	scratch_32 &= ~(0x000f0000);  in sdhci_pci_o2_fujin2_pci_init()
518 	scratch_32 |= 0x00080000;  in sdhci_pci_o2_fujin2_pci_init()
519 	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
562 	u32 scratch_32;  in sdhci_pci_o2_set_clock()  local
579 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
581 		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)  in sdhci_pci_o2_set_clock()
584 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
586 		if ((scratch_32 & 0xFFFF0000) != 0x25100000)  in sdhci_pci_o2_set_clock()
590 	pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);  in sdhci_pci_o2_set_clock()
591 	scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);  in sdhci_pci_o2_set_clock()
592 	pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);  in sdhci_pci_o2_set_clock()
682 	u32 scratch_32;  in sdhci_pci_o2_probe()  local
754 						    &scratch_32);  in sdhci_pci_o2_probe()
757 			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);  in sdhci_pci_o2_probe()
760 			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {  in sdhci_pci_o2_probe()
761 				scratch_32 = 0x25100000;  in sdhci_pci_o2_probe()
763 				o2_pci_set_baseclk(chip, scratch_32);  in sdhci_pci_o2_probe()
766 							    &scratch_32);  in sdhci_pci_o2_probe()
771 				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_pci_o2_probe()
774 						       scratch_32);  in sdhci_pci_o2_probe()
789 					    O2_SD_CLK_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
793 		scratch_32 &= ~(0xFF00);  in sdhci_pci_o2_probe()
794 		scratch_32 |= 0x07E0C800;  in sdhci_pci_o2_probe()
796 				       O2_SD_CLK_SETTING, scratch_32);  in sdhci_pci_o2_probe()
799 					    O2_SD_CLKREQ, &scratch_32);  in sdhci_pci_o2_probe()
802 		scratch_32 |= 0x3;  in sdhci_pci_o2_probe()
803 		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);  in sdhci_pci_o2_probe()
806 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
810 		scratch_32 &= ~(0x1F3F070E);  in sdhci_pci_o2_probe()
811 		scratch_32 |= 0x18270106;  in sdhci_pci_o2_probe()
813 				       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
817 					    O2_SD_CAP_REG2, &scratch_32);  in sdhci_pci_o2_probe()
820 		scratch_32 &= ~(0xE0);  in sdhci_pci_o2_probe()
822 				       O2_SD_CAP_REG2, scratch_32);  in sdhci_pci_o2_probe()
847 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
851 		if ((scratch_32 & 0xff000000) == 0x01000000) {  in sdhci_pci_o2_probe()
852 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
853 			scratch_32 |= 0x1F340000;  in sdhci_pci_o2_probe()
856 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
858 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
859 			scratch_32 |= 0x25100000;  in sdhci_pci_o2_probe()
862 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
866 						    &scratch_32);  in sdhci_pci_o2_probe()
869 			scratch_32 |= (1 << 22);  in sdhci_pci_o2_probe()
871 					       O2_SD_FUNC_REG4, scratch_32);  in sdhci_pci_o2_probe()