263 	u32 reg_value;  in update_config_from_hw()  local
267 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR);  in update_config_from_hw()
268 	xsdfec->config.order = reg_value;  in update_config_from_hw()
278 	reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);  in update_config_from_hw()
279 	xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;  in update_config_from_hw()
281 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);  in update_config_from_hw()
283 		(reg_value & XSDFEC_ECC_ISR_MASK) > 0;  in update_config_from_hw()
285 	reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);  in update_config_from_hw()
286 	sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;  in update_config_from_hw()
437 	u32 reg_value;  in xsdfec_get_turbo()  local
445 	reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR);  in xsdfec_get_turbo()
447 	turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >>  in xsdfec_get_turbo()
449 	turbo_params.alg = reg_value & 0x1;  in xsdfec_get_turbo()
780 	u32 reg_value;  in xsdfec_is_active()  local
784 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR);  in xsdfec_is_active()
786 	is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET);  in xsdfec_is_active()
830 	u32 reg_value;  in xsdfec_cfg_axi_streams()  local
847 	reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB;  in xsdfec_cfg_axi_streams()
848 	reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB;  in xsdfec_cfg_axi_streams()
849 	reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB;  in xsdfec_cfg_axi_streams()
850 	reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB;  in xsdfec_cfg_axi_streams()
852 	xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value);  in xsdfec_cfg_axi_streams()