477 struct cxl_afu {  struct
478 	struct cxl_afu_native *native;  argument
479 	struct cxl_afu_guest *guest;  argument
480 	irq_hw_number_t serr_hwirq;
481 	unsigned int serr_virq;
482 	char *psl_irq_name;
483 	char *err_irq_name;
484 	void __iomem *p2n_mmio;
485 	phys_addr_t psn_phys;
486 	u64 pp_size;
488 	struct cxl *adapter;
489 	struct device dev;
490 	struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
491 	struct device *chardev_s, *chardev_m, *chardev_d;
492 	struct idr contexts_idr;
493 	struct dentry *debugfs;
494 	struct mutex contexts_lock;
495 	spinlock_t afu_cntl_lock;
498 	atomic_t configured_state;
501 	u64 eb_len, eb_offset;
502 	struct bin_attribute attr_eb;
505 	struct pci_controller *phb;
507 	int pp_irqs;
508 	int irqs_max;
509 	int num_procs;
510 	int max_procs_virtualised;
511 	int slice;
512 	int modes_supported;
513 	int current_mode;
514 	int crs_num;
515 	u64 crs_len;
516 	u64 crs_offset;
517 	struct list_head crs;
541 	struct cxl_afu *afu;  argument