Lines Matching refs:ldr
53 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
54 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
57 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
60 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
63 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
66 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
69 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
72 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
75 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
78 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
81 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
84 ldr r1, [r0, #EMIF_COS_CONFIG]
87 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
90 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
93 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
96 ldr r1, [r0, #EMIF_OCP_CONFIG]
99 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
103 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
106 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
109 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
112 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
115 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
118 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
126 ldr r1, [r3, r5]
145 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
146 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
149 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
153 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
157 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
161 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
165 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
169 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
172 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
175 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
178 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
181 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
184 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
187 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
190 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
194 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
197 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
200 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
203 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
206 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
209 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
212 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
223 ldr r1, [r3, r5]
236 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
240 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
256 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
258 ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
260 ldr r2, [r0, #EMIF_SDRAM_CONFIG]
280 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
299 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
300 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
302 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
319 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
320 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
330 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
338 1: ldr r1, [r0, #EMIF_STATUS]
356 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
357 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
359 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
364 1: ldr r1, [r0, #EMIF_STATUS]