116 static struct vpss_oper_config oper_cfg;  variable
121 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in bl_regr()
126 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in bl_regw()
131 	return __raw_readl(oper_cfg.vpss_regs_base1 + offset);  in vpss_regr()
136 	__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);  in vpss_regw()
142 	return __raw_readl(oper_cfg.vpss_regs_base0 + offset);  in isp5_read()
148 	__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);  in isp5_write()
170 	if (!oper_cfg.hw_ops.dma_complete_interrupt)  in vpss_dma_complete_interrupt()
172 	return oper_cfg.hw_ops.dma_complete_interrupt();  in vpss_dma_complete_interrupt()
178 	if (!oper_cfg.hw_ops.select_ccdc_source)  in vpss_select_ccdc_source()
181 	oper_cfg.hw_ops.select_ccdc_source(src_sel);  in vpss_select_ccdc_source()
203 	if (!oper_cfg.hw_ops.set_sync_pol)  in vpss_set_sync_pol()
206 	oper_cfg.hw_ops.set_sync_pol(sync);  in vpss_set_sync_pol()
212 	if (!oper_cfg.hw_ops.clear_wbl_overflow)  in vpss_clear_wbl_overflow()
215 	return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);  in vpss_clear_wbl_overflow()
256 	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);  in dm355_enable_clock()
264 	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);  in dm355_enable_clock()
340 	spin_lock_irqsave(&oper_cfg.vpss_lock, flags);  in dm365_enable_clock()
349 	spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);  in dm365_enable_clock()
356 	if (!oper_cfg.hw_ops.enable_clock)  in vpss_enable_clock()
359 	return oper_cfg.hw_ops.enable_clock(clock_sel, en);  in vpss_enable_clock()
377 	if (!oper_cfg.hw_ops.set_pg_frame_size)  in vpss_set_pg_frame_size()
380 	oper_cfg.hw_ops.set_pg_frame_size(frame_size);  in vpss_set_pg_frame_size()
404 		oper_cfg.platform = DM355;  in vpss_probe()
406 		oper_cfg.platform = DM365;  in vpss_probe()
408 		oper_cfg.platform = DM644X;  in vpss_probe()
415 	oper_cfg.vpss_regs_base0 = devm_platform_ioremap_resource(pdev, 0);  in vpss_probe()
416 	if (IS_ERR(oper_cfg.vpss_regs_base0))  in vpss_probe()
417 		return PTR_ERR(oper_cfg.vpss_regs_base0);  in vpss_probe()
419 	if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {  in vpss_probe()
420 		oper_cfg.vpss_regs_base1 = devm_platform_ioremap_resource(pdev, 1);  in vpss_probe()
421 		if (IS_ERR(oper_cfg.vpss_regs_base1))  in vpss_probe()
422 			return PTR_ERR(oper_cfg.vpss_regs_base1);  in vpss_probe()
425 	if (oper_cfg.platform == DM355) {  in vpss_probe()
426 		oper_cfg.hw_ops.enable_clock = dm355_enable_clock;  in vpss_probe()
427 		oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;  in vpss_probe()
431 	} else if (oper_cfg.platform == DM365) {  in vpss_probe()
432 		oper_cfg.hw_ops.enable_clock = dm365_enable_clock;  in vpss_probe()
433 		oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;  in vpss_probe()
449 		oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;  in vpss_probe()
455 	spin_lock_init(&oper_cfg.vpss_lock);  in vpss_probe()
496 	iounmap(oper_cfg.vpss_regs_base2);  in vpss_exit()
507 	oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);  in vpss_init()
508 	if (unlikely(!oper_cfg.vpss_regs_base2)) {  in vpss_init()
514 	       VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);  in vpss_init()
523 	iounmap(oper_cfg.vpss_regs_base2);  in vpss_init()