Lines Matching refs:state
51 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
65 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg) in s5h1420_readreg() argument
70 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 }, in s5h1420_readreg()
71 { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, in s5h1420_readreg()
72 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 }, in s5h1420_readreg()
76 b[1] = state->shadow[(reg - 1) & 0xff]; in s5h1420_readreg()
78 if (state->config->repeated_start_workaround) { in s5h1420_readreg()
79 ret = i2c_transfer(state->i2c, msg, 3); in s5h1420_readreg()
83 ret = i2c_transfer(state->i2c, &msg[1], 1); in s5h1420_readreg()
86 ret = i2c_transfer(state->i2c, &msg[2], 1); in s5h1420_readreg()
96 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) in s5h1420_writereg() argument
99 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; in s5h1420_writereg()
103 err = i2c_transfer(state->i2c, &msg, 1); in s5h1420_writereg()
108 state->shadow[reg] = data; in s5h1420_writereg()
116 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_voltage() local
122 s5h1420_writereg(state, 0x3c, in s5h1420_set_voltage()
123 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02); in s5h1420_set_voltage()
127 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03); in s5h1420_set_voltage()
131 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd); in s5h1420_set_voltage()
142 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_tone() local
147 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
148 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08); in s5h1420_set_tone()
152 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
153 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); in s5h1420_set_tone()
164 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_send_master_cmd() local
175 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_master_cmd()
176 s5h1420_writereg(state, 0x3b, 0x02); in s5h1420_send_master_cmd()
181 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]); in s5h1420_send_master_cmd()
185 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | in s5h1420_send_master_cmd()
191 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_master_cmd()
200 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_master_cmd()
209 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_recv_slave_reply() local
217 val = s5h1420_readreg(state, 0x3b); in s5h1420_recv_slave_reply()
218 …s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive … in s5h1420_recv_slave_reply()
224 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */ in s5h1420_recv_slave_reply()
236 if (s5h1420_readreg(state, 0x49)) { in s5h1420_recv_slave_reply()
242 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4; in s5h1420_recv_slave_reply()
251 reply->msg[i] = s5h1420_readreg(state, 0x3d + i); in s5h1420_recv_slave_reply()
256 s5h1420_writereg(state, 0x3b, val); in s5h1420_recv_slave_reply()
264 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_send_burst() local
270 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_burst()
271 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01); in s5h1420_send_burst()
275 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04); in s5h1420_send_burst()
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); in s5h1420_send_burst()
285 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_burst()
294 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_burst()
299 static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state) in s5h1420_get_status_bits() argument
304 val = s5h1420_readreg(state, 0x14); in s5h1420_get_status_bits()
309 val = s5h1420_readreg(state, 0x36); in s5h1420_get_status_bits()
323 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_status() local
332 *status = s5h1420_get_status_bits(state); in s5h1420_read_status()
337 val = s5h1420_readreg(state, Vit10); in s5h1420_read_status()
340 s5h1420_writereg(state, Vit09, 0x13); in s5h1420_read_status()
342 s5h1420_writereg(state, Vit09, 0x1b); in s5h1420_read_status()
346 *status = s5h1420_get_status_bits(state); in s5h1420_read_status()
351 if ((*status & FE_HAS_LOCK) && !state->postlocked) { in s5h1420_read_status()
354 u32 tmp = s5h1420_getsymbolrate(state); in s5h1420_read_status()
355 switch (s5h1420_readreg(state, Vit10) & 0x07) { in s5h1420_read_status()
368 tmp = state->fclk / tmp; in s5h1420_read_status()
390 s5h1420_writereg(state, FEC01, 0x18); in s5h1420_read_status()
391 s5h1420_writereg(state, FEC01, 0x10); in s5h1420_read_status()
392 s5h1420_writereg(state, FEC01, val); in s5h1420_read_status()
395 val = s5h1420_readreg(state, Mpeg02); in s5h1420_read_status()
396 s5h1420_writereg(state, Mpeg02, val | (1 << 6)); in s5h1420_read_status()
399 val = s5h1420_readreg(state, QPSK01) & 0x7f; in s5h1420_read_status()
400 s5h1420_writereg(state, QPSK01, val); in s5h1420_read_status()
404 if (s5h1420_getsymbolrate(state) >= 20000000) { in s5h1420_read_status()
405 s5h1420_writereg(state, Loop04, 0x8a); in s5h1420_read_status()
406 s5h1420_writereg(state, Loop05, 0x6a); in s5h1420_read_status()
408 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_read_status()
409 s5h1420_writereg(state, Loop05, 0x27); in s5h1420_read_status()
413 state->postlocked = 1; in s5h1420_read_status()
423 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_ber() local
425 s5h1420_writereg(state, 0x46, 0x1d); in s5h1420_read_ber()
428 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ber()
435 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_signal_strength() local
437 u8 val = s5h1420_readreg(state, 0x15); in s5h1420_read_signal_strength()
446 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_ucblocks() local
448 s5h1420_writereg(state, 0x46, 0x1f); in s5h1420_read_ucblocks()
451 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ucblocks()
456 static void s5h1420_reset(struct s5h1420_state* state) in s5h1420_reset() argument
459 s5h1420_writereg (state, 0x01, 0x08); in s5h1420_reset()
460 s5h1420_writereg (state, 0x01, 0x00); in s5h1420_reset()
464 static void s5h1420_setsymbolrate(struct s5h1420_state* state, in s5h1420_setsymbolrate() argument
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
479 v = s5h1420_readreg(state, Loop01); in s5h1420_setsymbolrate()
480 s5h1420_writereg(state, Loop01, v & 0x7f); in s5h1420_setsymbolrate()
481 s5h1420_writereg(state, Tnco01, val >> 16); in s5h1420_setsymbolrate()
482 s5h1420_writereg(state, Tnco02, val >> 8); in s5h1420_setsymbolrate()
483 s5h1420_writereg(state, Tnco03, val & 0xff); in s5h1420_setsymbolrate()
484 s5h1420_writereg(state, Loop01, v | 0x80); in s5h1420_setsymbolrate()
488 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state) in s5h1420_getsymbolrate() argument
490 return state->symbol_rate; in s5h1420_getsymbolrate()
493 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset) in s5h1420_setfreqoffset() argument
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
506 v = s5h1420_readreg(state, Loop01); in s5h1420_setfreqoffset()
507 s5h1420_writereg(state, Loop01, v & 0xbf); in s5h1420_setfreqoffset()
508 s5h1420_writereg(state, Pnco01, val >> 16); in s5h1420_setfreqoffset()
509 s5h1420_writereg(state, Pnco02, val >> 8); in s5h1420_setfreqoffset()
510 s5h1420_writereg(state, Pnco03, val & 0xff); in s5h1420_setfreqoffset()
511 s5h1420_writereg(state, Loop01, v | 0x40); in s5h1420_setfreqoffset()
515 static int s5h1420_getfreqoffset(struct s5h1420_state* state) in s5h1420_getfreqoffset() argument
519 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08); in s5h1420_getfreqoffset()
520 val = s5h1420_readreg(state, 0x0e) << 16; in s5h1420_getfreqoffset()
521 val |= s5h1420_readreg(state, 0x0f) << 8; in s5h1420_getfreqoffset()
522 val |= s5h1420_readreg(state, 0x10); in s5h1420_getfreqoffset()
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
535 static void s5h1420_setfec_inversion(struct s5h1420_state* state, in s5h1420_setfec_inversion() argument
544 inversion = state->config->invert ? 0x08 : 0; in s5h1420_setfec_inversion()
546 inversion = state->config->invert ? 0 : 0x08; in s5h1420_setfec_inversion()
589 s5h1420_writereg(state, Vit08, vit08); in s5h1420_setfec_inversion()
590 s5h1420_writereg(state, Vit09, vit09); in s5h1420_setfec_inversion()
594 static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state) in s5h1420_getfec() argument
596 switch(s5h1420_readreg(state, 0x32) & 0x07) { in s5h1420_getfec()
620 s5h1420_getinversion(struct s5h1420_state *state) in s5h1420_getinversion() argument
622 if (s5h1420_readreg(state, 0x32) & 0x08) in s5h1420_getinversion()
631 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_frontend() local
639 frequency_delta = p->frequency - state->tunedfreq; in s5h1420_set_frontend()
643 (state->fec_inner == p->fec_inner) && in s5h1420_set_frontend()
644 (state->symbol_rate == p->symbol_rate)) { in s5h1420_set_frontend()
654 s5h1420_setfreqoffset(state, p->frequency - tmp); in s5h1420_set_frontend()
656 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
664 s5h1420_reset(state); in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
672 state->fclk = 86000000; in s5h1420_set_frontend()
674 state->fclk = 88000000; in s5h1420_set_frontend()
676 state->fclk = 44000000; in s5h1420_set_frontend()
678 …dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1)… in s5h1420_set_frontend()
679 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); in s5h1420_set_frontend()
680 s5h1420_writereg(state, PLL02, 0x40); in s5h1420_set_frontend()
681 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); in s5h1420_set_frontend()
685 s5h1420_writereg(state, QPSK01, 0xae | 0x10); in s5h1420_set_frontend()
687 s5h1420_writereg(state, QPSK01, 0xac | 0x10); in s5h1420_set_frontend()
690 s5h1420_writereg(state, CON_1, 0x00); in s5h1420_set_frontend()
691 s5h1420_writereg(state, QPSK02, 0x00); in s5h1420_set_frontend()
692 s5h1420_writereg(state, Pre01, 0xb0); in s5h1420_set_frontend()
694 s5h1420_writereg(state, Loop01, 0xF0); in s5h1420_set_frontend()
695 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ in s5h1420_set_frontend()
696 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ in s5h1420_set_frontend()
698 s5h1420_writereg(state, Loop04, 0x79); in s5h1420_set_frontend()
700 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_set_frontend()
701 s5h1420_writereg(state, Loop05, 0x6b); in s5h1420_set_frontend()
704 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); in s5h1420_set_frontend()
706 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); in s5h1420_set_frontend()
708 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); in s5h1420_set_frontend()
710 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */ in s5h1420_set_frontend()
712 s5h1420_writereg(state, Sync01, 0x33); in s5h1420_set_frontend()
713 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity); in s5h1420_set_frontend()
714 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */ in s5h1420_set_frontend()
715 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */ in s5h1420_set_frontend()
717 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */ in s5h1420_set_frontend()
718 s5h1420_writereg(state, DiS03, 0x00); in s5h1420_set_frontend()
719 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */ in s5h1420_set_frontend()
726 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
730 s5h1420_setsymbolrate(state, p); in s5h1420_set_frontend()
731 s5h1420_setfec_inversion(state, p); in s5h1420_set_frontend()
734 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1); in s5h1420_set_frontend()
736 state->fec_inner = p->fec_inner; in s5h1420_set_frontend()
737 state->symbol_rate = p->symbol_rate; in s5h1420_set_frontend()
738 state->postlocked = 0; in s5h1420_set_frontend()
739 state->tunedfreq = p->frequency; in s5h1420_set_frontend()
748 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_get_frontend() local
750 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state); in s5h1420_get_frontend()
751 p->inversion = s5h1420_getinversion(state); in s5h1420_get_frontend()
752 p->symbol_rate = s5h1420_getsymbolrate(state); in s5h1420_get_frontend()
753 p->fec_inner = s5h1420_getfec(state); in s5h1420_get_frontend()
793 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_i2c_gate_ctrl() local
796 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1); in s5h1420_i2c_gate_ctrl()
798 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe); in s5h1420_i2c_gate_ctrl()
803 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_init() local
806 state->CON_1_val = state->config->serial_mpeg << 4; in s5h1420_init()
807 s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_init()
809 s5h1420_reset(state); in s5h1420_init()
816 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_sleep() local
817 state->CON_1_val = 0x12; in s5h1420_sleep()
818 return s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_sleep()
823 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_release() local
824 i2c_del_adapter(&state->tuner_i2c_adapter); in s5h1420_release()
825 kfree(state); in s5h1420_release()
835 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap); in s5h1420_tuner_i2c_tuner_xfer() local
837 …u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition… in s5h1420_tuner_i2c_tuner_xfer()
848 m[0].addr = state->config->demod_address; in s5h1420_tuner_i2c_tuner_xfer()
854 return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO; in s5h1420_tuner_i2c_tuner_xfer()
864 struct s5h1420_state *state = fe->demodulator_priv; in s5h1420_get_tuner_i2c_adapter() local
865 return &state->tuner_i2c_adapter; in s5h1420_get_tuner_i2c_adapter()
875 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL); in s5h1420_attach() local
878 if (state == NULL) in s5h1420_attach()
882 state->config = config; in s5h1420_attach()
883 state->i2c = i2c; in s5h1420_attach()
884 state->postlocked = 0; in s5h1420_attach()
885 state->fclk = 88000000; in s5h1420_attach()
886 state->tunedfreq = 0; in s5h1420_attach()
887 state->fec_inner = FEC_NONE; in s5h1420_attach()
888 state->symbol_rate = 0; in s5h1420_attach()
891 i = s5h1420_readreg(state, ID01); in s5h1420_attach()
895 memset(state->shadow, 0xff, sizeof(state->shadow)); in s5h1420_attach()
898 state->shadow[i] = s5h1420_readreg(state, i); in s5h1420_attach()
901 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops)); in s5h1420_attach()
902 state->frontend.demodulator_priv = state; in s5h1420_attach()
905 strscpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", in s5h1420_attach()
906 sizeof(state->tuner_i2c_adapter.name)); in s5h1420_attach()
907 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo; in s5h1420_attach()
908 state->tuner_i2c_adapter.algo_data = NULL; in s5h1420_attach()
909 i2c_set_adapdata(&state->tuner_i2c_adapter, state); in s5h1420_attach()
910 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { in s5h1420_attach()
915 return &state->frontend; in s5h1420_attach()
918 kfree(state); in s5h1420_attach()