Lines Matching refs:state
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
29 static int set_qam_standard(struct drxk_state *state,
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
33 static int set_dvbt_standard(struct drxk_state *state,
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state) in is_dvbt() argument
45 return state->m_operation_mode == OM_DVBT; in is_dvbt()
48 static bool is_qam(struct drxk_state *state) in is_qam() argument
50 return state->m_operation_mode == OM_QAM_ITU_A || in is_qam()
51 state->m_operation_mode == OM_QAM_ITU_B || in is_qam()
52 state->m_operation_mode == OM_QAM_ITU_C; in is_qam()
94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
191 static int drxk_i2c_lock(struct drxk_state *state) in drxk_i2c_lock() argument
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_lock()
194 state->drxk_i2c_exclusive_lock = true; in drxk_i2c_lock()
199 static void drxk_i2c_unlock(struct drxk_state *state) in drxk_i2c_unlock() argument
201 if (!state->drxk_i2c_exclusive_lock) in drxk_i2c_unlock()
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_unlock()
205 state->drxk_i2c_exclusive_lock = false; in drxk_i2c_unlock()
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, in drxk_i2c_transfer() argument
211 if (state->drxk_i2c_exclusive_lock) in drxk_i2c_transfer()
212 return __i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
214 return i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) in i2c_read1() argument
223 return drxk_i2c_transfer(state, msgs, 1); in i2c_read1()
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) in i2c_write() argument
239 status = drxk_i2c_transfer(state, &msg, 1); in i2c_write()
249 static int i2c_read(struct drxk_state *state, in i2c_read() argument
260 status = drxk_i2c_transfer(state, msgs, 2); in i2c_read()
283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) in read16_flags() argument
286 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
288 if (state->single_master) in read16_flags()
303 status = i2c_read(state, adr, mm1, len, mm2, 2); in read16_flags()
312 static int read16(struct drxk_state *state, u32 reg, u16 *data) in read16() argument
314 return read16_flags(state, reg, data, 0); in read16()
317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) in read32_flags() argument
320 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
322 if (state->single_master) in read32_flags()
337 status = i2c_read(state, adr, mm1, len, mm2, 4); in read32_flags()
347 static int read32(struct drxk_state *state, u32 reg, u32 *data) in read32() argument
349 return read32_flags(state, reg, data, 0); in read32()
352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) in write16_flags() argument
354 u8 adr = state->demod_address, mm[6], len; in write16_flags()
356 if (state->single_master) in write16_flags()
373 return i2c_write(state, adr, mm, len + 2); in write16_flags()
376 static int write16(struct drxk_state *state, u32 reg, u16 data) in write16() argument
378 return write16_flags(state, reg, data, 0); in write16()
381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) in write32_flags() argument
383 u8 adr = state->demod_address, mm[8], len; in write32_flags()
385 if (state->single_master) in write32_flags()
404 return i2c_write(state, adr, mm, len + 4); in write32_flags()
407 static int write32(struct drxk_state *state, u32 reg, u32 data) in write32() argument
409 return write32_flags(state, reg, data, 0); in write32()
412 static int write_block(struct drxk_state *state, u32 address, in write_block() argument
418 if (state->single_master) in write_block()
422 int chunk = blk_size > state->m_chunk_size ? in write_block()
423 state->m_chunk_size : blk_size; in write_block()
424 u8 *adr_buf = &state->chunk[0]; in write_block()
434 if (chunk == state->m_chunk_size) in write_block()
442 memcpy(&state->chunk[adr_length], p_block, chunk); in write_block()
451 status = i2c_write(state, state->demod_address, in write_block()
452 &state->chunk[0], chunk + adr_length); in write_block()
469 static int power_up_device(struct drxk_state *state) in power_up_device() argument
477 status = i2c_read1(state, state->demod_address, &data); in power_up_device()
481 status = i2c_write(state, state->demod_address, in power_up_device()
487 status = i2c_read1(state, state->demod_address, in power_up_device()
496 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); in power_up_device()
499 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in power_up_device()
503 status = write16(state, SIO_CC_PLL_LOCK__A, 1); in power_up_device()
507 state->m_current_power_mode = DRX_POWER_UP; in power_up_device()
517 static int init_state(struct drxk_state *state) in init_state() argument
573 state->m_has_lna = false; in init_state()
574 state->m_has_dvbt = false; in init_state()
575 state->m_has_dvbc = false; in init_state()
576 state->m_has_atv = false; in init_state()
577 state->m_has_oob = false; in init_state()
578 state->m_has_audio = false; in init_state()
580 if (!state->m_chunk_size) in init_state()
581 state->m_chunk_size = 124; in init_state()
583 state->m_osc_clock_freq = 0; in init_state()
584 state->m_smart_ant_inverted = false; in init_state()
585 state->m_b_p_down_open_bridge = false; in init_state()
588 state->m_sys_clock_freq = 151875; in init_state()
591 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * in init_state()
594 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
595 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
596 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_state()
598 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
600 state->m_b_power_down = (ul_power_down != 0); in init_state()
602 state->m_drxk_a3_patch_code = false; in init_state()
606 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; in init_state()
607 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; in init_state()
608 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; in init_state()
609 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; in init_state()
610 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; in init_state()
611 state->m_vsb_pga_cfg = 140; in init_state()
614 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; in init_state()
615 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; in init_state()
616 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; in init_state()
617 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; in init_state()
618 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; in init_state()
619 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; in init_state()
620 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; in init_state()
621 state->m_vsb_pre_saw_cfg.reference = 0x07; in init_state()
622 state->m_vsb_pre_saw_cfg.use_pre_saw = true; in init_state()
624 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
625 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
627 state->m_Quality83percent = ulQual83; in init_state()
628 state->m_Quality93percent = ulQual93; in init_state()
632 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; in init_state()
633 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; in init_state()
634 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; in init_state()
635 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; in init_state()
636 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; in init_state()
639 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; in init_state()
640 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; in init_state()
641 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; in init_state()
642 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; in init_state()
643 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; in init_state()
644 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; in init_state()
645 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; in init_state()
646 state->m_atv_pre_saw_cfg.reference = 0x04; in init_state()
647 state->m_atv_pre_saw_cfg.use_pre_saw = true; in init_state()
651 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
652 state->m_dvbt_rf_agc_cfg.output_level = 0; in init_state()
653 state->m_dvbt_rf_agc_cfg.min_output_level = 0; in init_state()
654 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; in init_state()
655 state->m_dvbt_rf_agc_cfg.top = 0x2100; in init_state()
656 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; in init_state()
657 state->m_dvbt_rf_agc_cfg.speed = 1; in init_state()
661 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
662 state->m_dvbt_if_agc_cfg.output_level = 0; in init_state()
663 state->m_dvbt_if_agc_cfg.min_output_level = 0; in init_state()
664 state->m_dvbt_if_agc_cfg.max_output_level = 9000; in init_state()
665 state->m_dvbt_if_agc_cfg.top = 13424; in init_state()
666 state->m_dvbt_if_agc_cfg.cut_off_current = 0; in init_state()
667 state->m_dvbt_if_agc_cfg.speed = 3; in init_state()
668 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; in init_state()
669 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; in init_state()
672 state->m_dvbt_pre_saw_cfg.reference = 4; in init_state()
673 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; in init_state()
676 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
677 state->m_qam_rf_agc_cfg.output_level = 0; in init_state()
678 state->m_qam_rf_agc_cfg.min_output_level = 6023; in init_state()
679 state->m_qam_rf_agc_cfg.max_output_level = 27000; in init_state()
680 state->m_qam_rf_agc_cfg.top = 0x2380; in init_state()
681 state->m_qam_rf_agc_cfg.cut_off_current = 4000; in init_state()
682 state->m_qam_rf_agc_cfg.speed = 3; in init_state()
685 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
686 state->m_qam_if_agc_cfg.output_level = 0; in init_state()
687 state->m_qam_if_agc_cfg.min_output_level = 0; in init_state()
688 state->m_qam_if_agc_cfg.max_output_level = 9000; in init_state()
689 state->m_qam_if_agc_cfg.top = 0x0511; in init_state()
690 state->m_qam_if_agc_cfg.cut_off_current = 0; in init_state()
691 state->m_qam_if_agc_cfg.speed = 3; in init_state()
692 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; in init_state()
693 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; in init_state()
695 state->m_qam_pga_cfg = 140; in init_state()
696 state->m_qam_pre_saw_cfg.reference = 4; in init_state()
697 state->m_qam_pre_saw_cfg.use_pre_saw = false; in init_state()
699 state->m_operation_mode = OM_NONE; in init_state()
700 state->m_drxk_state = DRXK_UNINITIALIZED; in init_state()
703 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */ in init_state()
704 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ in init_state()
705 state->m_invert_data = false; /* If TRUE; invert DATA signals */ in init_state()
706 state->m_invert_err = false; /* If TRUE; invert ERR signal */ in init_state()
707 state->m_invert_str = false; /* If TRUE; invert STR signals */ in init_state()
708 state->m_invert_val = false; /* If TRUE; invert VAL signals */ in init_state()
709 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ in init_state()
714 state->m_dvbt_bitrate = ul_dvbt_bitrate; in init_state()
715 state->m_dvbc_bitrate = ul_dvbc_bitrate; in init_state()
717 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); in init_state()
720 state->m_mpeg_ts_static_bitrate = 19392658; in init_state()
721 state->m_disable_te_ihandling = false; in init_state()
724 state->m_insert_rs_byte = true; in init_state()
726 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
728 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; in init_state()
729 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
731 state->m_demod_lock_time_out = ul_demod_lock_time_out; in init_state()
734 state->m_constellation = DRX_CONSTELLATION_AUTO; in init_state()
735 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; in init_state()
736 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ in init_state()
737 state->m_fec_rs_prescale = 1; in init_state()
739 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
740 state->m_agcfast_clip_ctrl_delay = 0; in init_state()
742 state->m_gpio_cfg = ul_gpio_cfg; in init_state()
744 state->m_b_power_down = false; in init_state()
745 state->m_current_power_mode = DRX_POWER_DOWN; in init_state()
747 state->m_rfmirror = (ul_rf_mirror == 0); in init_state()
748 state->m_if_agc_pol = false; in init_state()
752 static int drxx_open(struct drxk_state *state) in drxx_open() argument
761 status = write16(state, SCU_RAM_GPIO__A, in drxx_open()
766 status = read16(state, SIO_TOP_COMM_KEY__A, &key); in drxx_open()
769 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in drxx_open()
772 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); in drxx_open()
775 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); in drxx_open()
778 status = write16(state, SIO_TOP_COMM_KEY__A, key); in drxx_open()
785 static int get_device_capabilities(struct drxk_state *state) in get_device_capabilities() argument
796 status = write16(state, SCU_RAM_GPIO__A, in get_device_capabilities()
800 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in get_device_capabilities()
803 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); in get_device_capabilities()
806 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in get_device_capabilities()
816 state->m_osc_clock_freq = 27000; in get_device_capabilities()
820 state->m_osc_clock_freq = 20250; in get_device_capabilities()
824 state->m_osc_clock_freq = 20250; in get_device_capabilities()
834 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); in get_device_capabilities()
843 state->m_device_spin = DRXK_SPIN_A1; in get_device_capabilities()
847 state->m_device_spin = DRXK_SPIN_A2; in get_device_capabilities()
851 state->m_device_spin = DRXK_SPIN_A3; in get_device_capabilities()
855 state->m_device_spin = DRXK_SPIN_UNKNOWN; in get_device_capabilities()
863 state->m_has_lna = false; in get_device_capabilities()
864 state->m_has_oob = false; in get_device_capabilities()
865 state->m_has_atv = false; in get_device_capabilities()
866 state->m_has_audio = false; in get_device_capabilities()
867 state->m_has_dvbt = true; in get_device_capabilities()
868 state->m_has_dvbc = true; in get_device_capabilities()
869 state->m_has_sawsw = true; in get_device_capabilities()
870 state->m_has_gpio2 = false; in get_device_capabilities()
871 state->m_has_gpio1 = false; in get_device_capabilities()
872 state->m_has_irqn = false; in get_device_capabilities()
876 state->m_has_lna = false; in get_device_capabilities()
877 state->m_has_oob = false; in get_device_capabilities()
878 state->m_has_atv = true; in get_device_capabilities()
879 state->m_has_audio = false; in get_device_capabilities()
880 state->m_has_dvbt = true; in get_device_capabilities()
881 state->m_has_dvbc = false; in get_device_capabilities()
882 state->m_has_sawsw = true; in get_device_capabilities()
883 state->m_has_gpio2 = true; in get_device_capabilities()
884 state->m_has_gpio1 = true; in get_device_capabilities()
885 state->m_has_irqn = false; in get_device_capabilities()
889 state->m_has_lna = false; in get_device_capabilities()
890 state->m_has_oob = false; in get_device_capabilities()
891 state->m_has_atv = true; in get_device_capabilities()
892 state->m_has_audio = false; in get_device_capabilities()
893 state->m_has_dvbt = true; in get_device_capabilities()
894 state->m_has_dvbc = false; in get_device_capabilities()
895 state->m_has_sawsw = true; in get_device_capabilities()
896 state->m_has_gpio2 = true; in get_device_capabilities()
897 state->m_has_gpio1 = true; in get_device_capabilities()
898 state->m_has_irqn = false; in get_device_capabilities()
902 state->m_has_lna = false; in get_device_capabilities()
903 state->m_has_oob = false; in get_device_capabilities()
904 state->m_has_atv = true; in get_device_capabilities()
905 state->m_has_audio = true; in get_device_capabilities()
906 state->m_has_dvbt = true; in get_device_capabilities()
907 state->m_has_dvbc = false; in get_device_capabilities()
908 state->m_has_sawsw = true; in get_device_capabilities()
909 state->m_has_gpio2 = true; in get_device_capabilities()
910 state->m_has_gpio1 = true; in get_device_capabilities()
911 state->m_has_irqn = false; in get_device_capabilities()
915 state->m_has_lna = false; in get_device_capabilities()
916 state->m_has_oob = false; in get_device_capabilities()
917 state->m_has_atv = true; in get_device_capabilities()
918 state->m_has_audio = true; in get_device_capabilities()
919 state->m_has_dvbt = true; in get_device_capabilities()
920 state->m_has_dvbc = true; in get_device_capabilities()
921 state->m_has_sawsw = true; in get_device_capabilities()
922 state->m_has_gpio2 = true; in get_device_capabilities()
923 state->m_has_gpio1 = true; in get_device_capabilities()
924 state->m_has_irqn = false; in get_device_capabilities()
928 state->m_has_lna = false; in get_device_capabilities()
929 state->m_has_oob = false; in get_device_capabilities()
930 state->m_has_atv = true; in get_device_capabilities()
931 state->m_has_audio = true; in get_device_capabilities()
932 state->m_has_dvbt = true; in get_device_capabilities()
933 state->m_has_dvbc = true; in get_device_capabilities()
934 state->m_has_sawsw = true; in get_device_capabilities()
935 state->m_has_gpio2 = true; in get_device_capabilities()
936 state->m_has_gpio1 = true; in get_device_capabilities()
937 state->m_has_irqn = false; in get_device_capabilities()
941 state->m_has_lna = false; in get_device_capabilities()
942 state->m_has_oob = false; in get_device_capabilities()
943 state->m_has_atv = true; in get_device_capabilities()
944 state->m_has_audio = true; in get_device_capabilities()
945 state->m_has_dvbt = true; in get_device_capabilities()
946 state->m_has_dvbc = true; in get_device_capabilities()
947 state->m_has_sawsw = true; in get_device_capabilities()
948 state->m_has_gpio2 = true; in get_device_capabilities()
949 state->m_has_gpio1 = true; in get_device_capabilities()
950 state->m_has_irqn = false; in get_device_capabilities()
954 state->m_has_lna = false; in get_device_capabilities()
955 state->m_has_oob = false; in get_device_capabilities()
956 state->m_has_atv = true; in get_device_capabilities()
957 state->m_has_audio = false; in get_device_capabilities()
958 state->m_has_dvbt = true; in get_device_capabilities()
959 state->m_has_dvbc = true; in get_device_capabilities()
960 state->m_has_sawsw = true; in get_device_capabilities()
961 state->m_has_gpio2 = true; in get_device_capabilities()
962 state->m_has_gpio1 = true; in get_device_capabilities()
963 state->m_has_irqn = false; in get_device_capabilities()
974 state->m_osc_clock_freq / 1000, in get_device_capabilities()
975 state->m_osc_clock_freq % 1000); in get_device_capabilities()
985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) in hi_command() argument
993 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); in hi_command()
1001 ((state->m_hi_cfg_ctrl) & in hi_command()
1012 status = read16(state, SIO_HI_RA_RAM_CMD__A, in hi_command()
1017 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); in hi_command()
1026 static int hi_cfg_command(struct drxk_state *state) in hi_cfg_command() argument
1032 mutex_lock(&state->mutex); in hi_cfg_command()
1034 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, in hi_cfg_command()
1035 state->m_hi_cfg_timeout); in hi_cfg_command()
1038 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, in hi_cfg_command()
1039 state->m_hi_cfg_ctrl); in hi_cfg_command()
1042 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, in hi_cfg_command()
1043 state->m_hi_cfg_wake_up_key); in hi_cfg_command()
1046 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, in hi_cfg_command()
1047 state->m_hi_cfg_bridge_delay); in hi_cfg_command()
1050 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in hi_cfg_command()
1051 state->m_hi_cfg_timing_div); in hi_cfg_command()
1054 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, in hi_cfg_command()
1058 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); in hi_cfg_command()
1062 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in hi_cfg_command()
1064 mutex_unlock(&state->mutex); in hi_cfg_command()
1070 static int init_hi(struct drxk_state *state) in init_hi() argument
1074 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_hi()
1075 state->m_hi_cfg_timeout = 0x96FF; in init_hi()
1077 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_hi()
1079 return hi_cfg_command(state); in init_hi()
1082 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) in mpegts_configure_pins() argument
1091 state->m_enable_parallel ? "parallel" : "serial"); in mpegts_configure_pins()
1094 status = write16(state, SCU_RAM_GPIO__A, in mpegts_configure_pins()
1100 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in mpegts_configure_pins()
1106 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); in mpegts_configure_pins()
1109 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); in mpegts_configure_pins()
1112 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); in mpegts_configure_pins()
1115 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); in mpegts_configure_pins()
1118 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); in mpegts_configure_pins()
1121 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in mpegts_configure_pins()
1124 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in mpegts_configure_pins()
1127 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in mpegts_configure_pins()
1130 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in mpegts_configure_pins()
1133 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in mpegts_configure_pins()
1136 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in mpegts_configure_pins()
1139 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in mpegts_configure_pins()
1145 ((state->m_ts_data_strength << in mpegts_configure_pins()
1147 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << in mpegts_configure_pins()
1151 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); in mpegts_configure_pins()
1155 if (state->enable_merr_cfg) in mpegts_configure_pins()
1158 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); in mpegts_configure_pins()
1161 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); in mpegts_configure_pins()
1165 if (state->m_enable_parallel) { in mpegts_configure_pins()
1167 status = write16(state, SIO_PDR_MD1_CFG__A, in mpegts_configure_pins()
1171 status = write16(state, SIO_PDR_MD2_CFG__A, in mpegts_configure_pins()
1175 status = write16(state, SIO_PDR_MD3_CFG__A, in mpegts_configure_pins()
1179 status = write16(state, SIO_PDR_MD4_CFG__A, in mpegts_configure_pins()
1183 status = write16(state, SIO_PDR_MD5_CFG__A, in mpegts_configure_pins()
1187 status = write16(state, SIO_PDR_MD6_CFG__A, in mpegts_configure_pins()
1191 status = write16(state, SIO_PDR_MD7_CFG__A, in mpegts_configure_pins()
1196 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << in mpegts_configure_pins()
1200 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in mpegts_configure_pins()
1203 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in mpegts_configure_pins()
1206 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in mpegts_configure_pins()
1209 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in mpegts_configure_pins()
1212 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in mpegts_configure_pins()
1215 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in mpegts_configure_pins()
1218 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in mpegts_configure_pins()
1222 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); in mpegts_configure_pins()
1225 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); in mpegts_configure_pins()
1230 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); in mpegts_configure_pins()
1234 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in mpegts_configure_pins()
1241 static int mpegts_disable(struct drxk_state *state) in mpegts_disable() argument
1245 return mpegts_configure_pins(state, false); in mpegts_disable()
1248 static int bl_chain_cmd(struct drxk_state *state, in bl_chain_cmd() argument
1256 mutex_lock(&state->mutex); in bl_chain_cmd()
1257 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); in bl_chain_cmd()
1260 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); in bl_chain_cmd()
1263 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); in bl_chain_cmd()
1266 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in bl_chain_cmd()
1273 status = read16(state, SIO_BL_STATUS__A, &bl_status); in bl_chain_cmd()
1288 mutex_unlock(&state->mutex); in bl_chain_cmd()
1293 static int download_microcode(struct drxk_state *state, in download_microcode() argument
1346 status = write_block(state, address, block_size, p_src); in download_microcode()
1357 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) in dvbt_enable_ofdm_token_ring() argument
1372 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in dvbt_enable_ofdm_token_ring()
1378 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); in dvbt_enable_ofdm_token_ring()
1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in dvbt_enable_ofdm_token_ring()
1395 static int mpegts_stop(struct drxk_state *state) in mpegts_stop() argument
1404 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); in mpegts_stop()
1408 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); in mpegts_stop()
1413 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); in mpegts_stop()
1417 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); in mpegts_stop()
1426 static int scu_command(struct drxk_state *state, in scu_command() argument
1449 mutex_lock(&state->mutex); in scu_command()
1462 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1468 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); in scu_command()
1483 status = read16(state, SCU_RAM_PARAM_0__A - ii, in scu_command()
1522 mutex_unlock(&state->mutex); in scu_command()
1526 static int set_iqm_af(struct drxk_state *state, bool active) in set_iqm_af() argument
1534 status = read16(state, IQM_AF_STDBY__A, &data); in set_iqm_af()
1552 status = write16(state, IQM_AF_STDBY__A, data); in set_iqm_af()
1560 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) in ctrl_power_mode() argument
1593 if (state->m_current_power_mode == *mode) in ctrl_power_mode()
1597 if (state->m_current_power_mode != DRX_POWER_UP) { in ctrl_power_mode()
1598 status = power_up_device(state); in ctrl_power_mode()
1601 status = dvbt_enable_ofdm_token_ring(state, true); in ctrl_power_mode()
1618 switch (state->m_operation_mode) { in ctrl_power_mode()
1620 status = mpegts_stop(state); in ctrl_power_mode()
1623 status = power_down_dvbt(state, false); in ctrl_power_mode()
1629 status = mpegts_stop(state); in ctrl_power_mode()
1632 status = power_down_qam(state); in ctrl_power_mode()
1639 status = dvbt_enable_ofdm_token_ring(state, false); in ctrl_power_mode()
1642 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); in ctrl_power_mode()
1645 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in ctrl_power_mode()
1650 state->m_hi_cfg_ctrl |= in ctrl_power_mode()
1652 status = hi_cfg_command(state); in ctrl_power_mode()
1657 state->m_current_power_mode = *mode; in ctrl_power_mode()
1666 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) in power_down_dvbt() argument
1675 status = read16(state, SCU_COMM_EXEC__A, &data); in power_down_dvbt()
1680 status = scu_command(state, in power_down_dvbt()
1687 status = scu_command(state, in power_down_dvbt()
1696 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in power_down_dvbt()
1699 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in power_down_dvbt()
1702 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in power_down_dvbt()
1707 status = set_iqm_af(state, false); in power_down_dvbt()
1713 status = ctrl_power_mode(state, &power_mode); in power_down_dvbt()
1723 static int setoperation_mode(struct drxk_state *state, in setoperation_mode() argument
1736 status = write16(state, SCU_RAM_GPIO__A, in setoperation_mode()
1742 if (state->m_operation_mode == o_mode) in setoperation_mode()
1745 switch (state->m_operation_mode) { in setoperation_mode()
1750 status = mpegts_stop(state); in setoperation_mode()
1753 status = power_down_dvbt(state, true); in setoperation_mode()
1756 state->m_operation_mode = OM_NONE; in setoperation_mode()
1760 status = mpegts_stop(state); in setoperation_mode()
1763 status = power_down_qam(state); in setoperation_mode()
1766 state->m_operation_mode = OM_NONE; in setoperation_mode()
1780 state->m_operation_mode = o_mode; in setoperation_mode()
1781 status = set_dvbt_standard(state, o_mode); in setoperation_mode()
1788 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); in setoperation_mode()
1789 state->m_operation_mode = o_mode; in setoperation_mode()
1790 status = set_qam_standard(state, o_mode); in setoperation_mode()
1804 static int start(struct drxk_state *state, s32 offset_freq, in start() argument
1813 if (state->m_drxk_state != DRXK_STOPPED && in start()
1814 state->m_drxk_state != DRXK_DTV_STARTED) in start()
1817 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); in start()
1820 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; in start()
1824 switch (state->m_operation_mode) { in start()
1828 status = set_qam(state, i_freqk_hz, offsetk_hz); in start()
1831 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1835 status = mpegts_stop(state); in start()
1838 status = set_dvbt(state, i_freqk_hz, offsetk_hz); in start()
1841 status = dvbt_start(state); in start()
1844 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1855 static int shut_down(struct drxk_state *state) in shut_down() argument
1859 mpegts_stop(state); in shut_down()
1863 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_lock_status() argument
1875 switch (state->m_operation_mode) { in get_lock_status()
1879 status = get_qam_lock_status(state, p_lock_status); in get_lock_status()
1882 status = get_dvbt_lock_status(state, p_lock_status); in get_lock_status()
1886 state->m_operation_mode, __func__); in get_lock_status()
1895 static int mpegts_start(struct drxk_state *state) in mpegts_start() argument
1902 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); in mpegts_start()
1906 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); in mpegts_start()
1909 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); in mpegts_start()
1916 static int mpegts_dto_init(struct drxk_state *state) in mpegts_dto_init() argument
1923 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); in mpegts_dto_init()
1926 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); in mpegts_dto_init()
1929 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); in mpegts_dto_init()
1932 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); in mpegts_dto_init()
1935 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); in mpegts_dto_init()
1938 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); in mpegts_dto_init()
1941 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); in mpegts_dto_init()
1944 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); in mpegts_dto_init()
1949 status = write16(state, FEC_OC_OCR_INVERT__A, 0); in mpegts_dto_init()
1952 status = write16(state, FEC_OC_SNC_LWM__A, 2); in mpegts_dto_init()
1955 status = write16(state, FEC_OC_SNC_HWM__A, 12); in mpegts_dto_init()
1963 static int mpegts_dto_setup(struct drxk_state *state, in mpegts_dto_setup() argument
1983 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); in mpegts_dto_setup()
1986 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); in mpegts_dto_setup()
1991 if (state->m_insert_rs_byte) { in mpegts_dto_setup()
2002 if (!state->m_enable_parallel) { in mpegts_dto_setup()
2009 max_bit_rate = state->m_dvbt_bitrate; in mpegts_dto_setup()
2012 static_clk = state->m_dvbt_static_clk; in mpegts_dto_setup()
2018 max_bit_rate = state->m_dvbc_bitrate; in mpegts_dto_setup()
2019 static_clk = state->m_dvbc_static_clk; in mpegts_dto_setup()
2051 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) in mpegts_dto_setup()
2066 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); in mpegts_dto_setup()
2069 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); in mpegts_dto_setup()
2072 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); in mpegts_dto_setup()
2075 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); in mpegts_dto_setup()
2078 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); in mpegts_dto_setup()
2081 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); in mpegts_dto_setup()
2086 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); in mpegts_dto_setup()
2089 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, in mpegts_dto_setup()
2093 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); in mpegts_dto_setup()
2100 static int mpegts_configure_polarity(struct drxk_state *state) in mpegts_configure_polarity() argument
2115 if (state->m_invert_data) in mpegts_configure_polarity()
2118 if (state->m_invert_err) in mpegts_configure_polarity()
2121 if (state->m_invert_str) in mpegts_configure_polarity()
2124 if (state->m_invert_val) in mpegts_configure_polarity()
2127 if (state->m_invert_clk) in mpegts_configure_polarity()
2130 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); in mpegts_configure_polarity()
2135 static int set_agc_rf(struct drxk_state *state, in set_agc_rf() argument
2150 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2154 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2157 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2165 if (state->m_rf_agc_pol) in set_agc_rf()
2169 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2174 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in set_agc_rf()
2183 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in set_agc_rf()
2187 if (is_dvbt(state)) in set_agc_rf()
2188 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; in set_agc_rf()
2189 else if (is_qam(state)) in set_agc_rf()
2190 p_if_agc_settings = &state->m_qam_if_agc_cfg; in set_agc_rf()
2192 p_if_agc_settings = &state->m_atv_if_agc_cfg; in set_agc_rf()
2200 status = write16(state, in set_agc_rf()
2208 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, in set_agc_rf()
2214 status = write16(state, SCU_RAM_AGC_RF_MAX__A, in set_agc_rf()
2223 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2227 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2232 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2236 if (state->m_rf_agc_pol) in set_agc_rf()
2240 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2245 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); in set_agc_rf()
2250 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, in set_agc_rf()
2258 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2262 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2267 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2271 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2288 static int set_agc_if(struct drxk_state *state, in set_agc_if() argument
2301 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2305 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2309 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2317 if (state->m_if_agc_pol) in set_agc_if()
2321 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2326 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in set_agc_if()
2334 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in set_agc_if()
2338 if (is_qam(state)) in set_agc_if()
2339 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; in set_agc_if()
2341 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; in set_agc_if()
2345 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in set_agc_if()
2354 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2358 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2362 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2370 if (state->m_if_agc_pol) in set_agc_if()
2374 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2379 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in set_agc_if()
2388 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2392 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2397 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2401 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2409 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); in set_agc_if()
2416 static int get_qam_signal_to_noise(struct drxk_state *state, in get_qam_signal_to_noise() argument
2431 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); in get_qam_signal_to_noise()
2437 switch (state->props.modulation) { in get_qam_signal_to_noise()
2465 static int get_dvbt_signal_to_noise(struct drxk_state *state, in get_dvbt_signal_to_noise() argument
2485 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, in get_dvbt_signal_to_noise()
2489 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, in get_dvbt_signal_to_noise()
2493 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, in get_dvbt_signal_to_noise()
2497 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, in get_dvbt_signal_to_noise()
2507 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); in get_dvbt_signal_to_noise()
2516 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, in get_dvbt_signal_to_noise()
2569 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) in get_signal_to_noise() argument
2574 switch (state->m_operation_mode) { in get_signal_to_noise()
2576 return get_dvbt_signal_to_noise(state, p_signal_to_noise); in get_signal_to_noise()
2579 return get_qam_signal_to_noise(state, p_signal_to_noise); in get_signal_to_noise()
2587 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2621 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2624 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2630 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2654 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2666 status = get_qam_signal_to_noise(state, &signal_to_noise);
2670 switch (state->props.modulation) {
2701 static int get_quality(struct drxk_state *state, s32 *p_quality)
2705 switch (state->m_operation_mode) {
2707 return get_dvbt_quality(state, p_quality);
2709 return get_dvbc_quality(state, p_quality);
2731 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) in ConfigureI2CBridge() argument
2737 if (state->m_drxk_state == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2739 if (state->m_drxk_state == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2742 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2745 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, in ConfigureI2CBridge()
2750 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in ConfigureI2CBridge()
2755 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in ConfigureI2CBridge()
2761 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); in ConfigureI2CBridge()
2769 static int set_pre_saw(struct drxk_state *state, in set_pre_saw() argument
2780 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); in set_pre_saw()
2787 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, in bl_direct_cmd() argument
2798 mutex_lock(&state->mutex); in bl_direct_cmd()
2799 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); in bl_direct_cmd()
2802 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); in bl_direct_cmd()
2805 status = write16(state, SIO_BL_TGT_ADDR__A, offset); in bl_direct_cmd()
2808 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); in bl_direct_cmd()
2811 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); in bl_direct_cmd()
2814 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in bl_direct_cmd()
2820 status = read16(state, SIO_BL_STATUS__A, &bl_status); in bl_direct_cmd()
2833 mutex_unlock(&state->mutex); in bl_direct_cmd()
2838 static int adc_sync_measurement(struct drxk_state *state, u16 *count) in adc_sync_measurement() argument
2846 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); in adc_sync_measurement()
2849 status = write16(state, IQM_AF_START_LOCK__A, 1); in adc_sync_measurement()
2854 status = read16(state, IQM_AF_PHASE0__A, &data); in adc_sync_measurement()
2859 status = read16(state, IQM_AF_PHASE1__A, &data); in adc_sync_measurement()
2864 status = read16(state, IQM_AF_PHASE2__A, &data); in adc_sync_measurement()
2876 static int adc_synchronization(struct drxk_state *state) in adc_synchronization() argument
2883 status = adc_sync_measurement(state, &count); in adc_synchronization()
2891 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); in adc_synchronization()
2904 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); in adc_synchronization()
2907 status = adc_sync_measurement(state, &count); in adc_synchronization()
2920 static int set_frequency_shifter(struct drxk_state *state, in set_frequency_shifter() argument
2927 bool tuner_mirror = !state->m_b_mirror_freq_spect; in set_frequency_shifter()
2932 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); in set_frequency_shifter()
2943 if ((state->m_operation_mode == OM_QAM_ITU_A) || in set_frequency_shifter()
2944 (state->m_operation_mode == OM_QAM_ITU_C) || in set_frequency_shifter()
2945 (state->m_operation_mode == OM_DVBT)) in set_frequency_shifter()
2969 image_to_select = state->m_rfmirror ^ tuner_mirror ^ in set_frequency_shifter()
2971 state->m_iqm_fs_rate_ofs = in set_frequency_shifter()
2975 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; in set_frequency_shifter()
2979 status = write32(state, IQM_FS_RATE_OFS_LO__A, in set_frequency_shifter()
2980 state->m_iqm_fs_rate_ofs); in set_frequency_shifter()
2986 static int init_agc(struct drxk_state *state, bool is_dtv) in init_agc() argument
3016 if (!is_qam(state)) { in init_agc()
3018 __func__, state->m_operation_mode); in init_agc()
3036 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; in init_agc()
3038 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, in init_agc()
3043 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); in init_agc()
3046 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); in init_agc()
3049 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); in init_agc()
3052 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); in init_agc()
3055 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, in init_agc()
3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in init_agc()
3063 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); in init_agc()
3066 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); in init_agc()
3069 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); in init_agc()
3072 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); in init_agc()
3075 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); in init_agc()
3078 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); in init_agc()
3082 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, in init_agc()
3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, in init_agc()
3090 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); in init_agc()
3094 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); in init_agc()
3097 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in init_agc()
3100 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); in init_agc()
3104 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); in init_agc()
3107 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); in init_agc()
3110 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); in init_agc()
3113 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); in init_agc()
3116 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); in init_agc()
3119 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); in init_agc()
3122 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); in init_agc()
3125 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); in init_agc()
3128 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); in init_agc()
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); in init_agc()
3134 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); in init_agc()
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); in init_agc()
3140 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); in init_agc()
3143 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); in init_agc()
3146 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); in init_agc()
3149 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); in init_agc()
3152 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); in init_agc()
3155 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); in init_agc()
3158 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); in init_agc()
3163 status = read16(state, SCU_RAM_AGC_KI__A, &data); in init_agc()
3173 status = write16(state, SCU_RAM_AGC_KI__A, data); in init_agc()
3180 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) in dvbtqam_get_acc_pkt_err() argument
3186 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in dvbtqam_get_acc_pkt_err()
3188 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, in dvbtqam_get_acc_pkt_err()
3195 static int dvbt_sc_command(struct drxk_state *state, in dvbt_sc_command() argument
3207 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); in dvbt_sc_command()
3219 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); in dvbt_sc_command()
3231 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); in dvbt_sc_command()
3250 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); in dvbt_sc_command()
3254 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); in dvbt_sc_command()
3259 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); in dvbt_sc_command()
3272 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); in dvbt_sc_command()
3279 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); in dvbt_sc_command()
3296 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); in dvbt_sc_command()
3317 static int power_up_dvbt(struct drxk_state *state) in power_up_dvbt() argument
3323 status = ctrl_power_mode(state, &power_mode); in power_up_dvbt()
3329 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) in dvbt_ctrl_set_inc_enable() argument
3335 status = write16(state, IQM_CF_BYPASSDET__A, 0); in dvbt_ctrl_set_inc_enable()
3337 status = write16(state, IQM_CF_BYPASSDET__A, 1); in dvbt_ctrl_set_inc_enable()
3344 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) in dvbt_ctrl_set_fr_enable() argument
3352 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, in dvbt_ctrl_set_fr_enable()
3356 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); in dvbt_ctrl_set_fr_enable()
3364 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, in dvbt_ctrl_set_echo_threshold() argument
3371 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); in dvbt_ctrl_set_echo_threshold()
3392 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); in dvbt_ctrl_set_echo_threshold()
3399 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, in dvbt_ctrl_set_sqi_speed() argument
3414 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, in dvbt_ctrl_set_sqi_speed()
3432 static int dvbt_activate_presets(struct drxk_state *state) in dvbt_activate_presets() argument
3442 status = dvbt_ctrl_set_inc_enable(state, &setincenable); in dvbt_activate_presets()
3445 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); in dvbt_activate_presets()
3448 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); in dvbt_activate_presets()
3451 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); in dvbt_activate_presets()
3454 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, in dvbt_activate_presets()
3455 state->m_dvbt_if_agc_cfg.ingain_tgt_max); in dvbt_activate_presets()
3472 static int set_dvbt_standard(struct drxk_state *state, in set_dvbt_standard() argument
3481 power_up_dvbt(state); in set_dvbt_standard()
3483 switch_antenna_to_dvbt(state); in set_dvbt_standard()
3485 status = scu_command(state, in set_dvbt_standard()
3493 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt_standard()
3500 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in set_dvbt_standard()
3503 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in set_dvbt_standard()
3506 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in set_dvbt_standard()
3512 status = write16(state, IQM_AF_UPD_SEL__A, 1); in set_dvbt_standard()
3516 status = write16(state, IQM_AF_CLP_LEN__A, 0); in set_dvbt_standard()
3520 status = write16(state, IQM_AF_SNS_LEN__A, 0); in set_dvbt_standard()
3524 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in set_dvbt_standard()
3527 status = set_iqm_af(state, true); in set_dvbt_standard()
3531 status = write16(state, IQM_AF_AGC_RF__A, 0); in set_dvbt_standard()
3536 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ in set_dvbt_standard()
3539 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ in set_dvbt_standard()
3542 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ in set_dvbt_standard()
3546 status = write16(state, IQM_RC_STRETCH__A, 16); in set_dvbt_standard()
3549 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ in set_dvbt_standard()
3552 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ in set_dvbt_standard()
3555 status = write16(state, IQM_CF_SCALE__A, 1600); in set_dvbt_standard()
3558 status = write16(state, IQM_CF_SCALE_SH__A, 0); in set_dvbt_standard()
3563 status = write16(state, IQM_AF_CLP_TH__A, 448); in set_dvbt_standard()
3566 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ in set_dvbt_standard()
3570 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, in set_dvbt_standard()
3575 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ in set_dvbt_standard()
3578 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); in set_dvbt_standard()
3582 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); in set_dvbt_standard()
3585 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in set_dvbt_standard()
3590 status = adc_synchronization(state); in set_dvbt_standard()
3593 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); in set_dvbt_standard()
3598 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_dvbt_standard()
3602 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); in set_dvbt_standard()
3605 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); in set_dvbt_standard()
3610 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); in set_dvbt_standard()
3614 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); in set_dvbt_standard()
3619 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_dvbt_standard()
3623 if (!state->m_drxk_a3_rom_code) { in set_dvbt_standard()
3625 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, in set_dvbt_standard()
3626 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); in set_dvbt_standard()
3633 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); in set_dvbt_standard()
3636 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); in set_dvbt_standard()
3642 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ in set_dvbt_standard()
3648 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); in set_dvbt_standard()
3652 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); in set_dvbt_standard()
3656 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); in set_dvbt_standard()
3661 status = mpegts_dto_setup(state, OM_DVBT); in set_dvbt_standard()
3665 status = dvbt_activate_presets(state); in set_dvbt_standard()
3681 static int dvbt_start(struct drxk_state *state) in dvbt_start() argument
3691 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, in dvbt_start()
3697 status = mpegts_start(state); in dvbt_start()
3700 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in dvbt_start()
3718 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, in set_dvbt() argument
3731 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt()
3738 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_dvbt()
3743 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in set_dvbt()
3746 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in set_dvbt()
3752 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); in set_dvbt()
3759 switch (state->props.transmission_mode) { in set_dvbt()
3771 switch (state->props.guard_interval) { in set_dvbt()
3789 switch (state->props.hierarchy) { in set_dvbt()
3806 switch (state->props.modulation) { in set_dvbt()
3841 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); in set_dvbt()
3847 switch (state->props.code_rate_HP) { in set_dvbt()
3880 switch (state->props.bandwidth_hz) { in set_dvbt()
3882 state->props.bandwidth_hz = 8000000; in set_dvbt()
3886 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3891 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3895 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3899 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3903 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3910 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3915 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3919 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3923 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3934 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3939 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3943 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3947 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3975 ((state->m_sys_clock_freq * in set_dvbt()
3988 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); in set_dvbt()
3999 status = set_frequency_shifter(state, intermediate_freqk_hz, in set_dvbt()
4007 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_dvbt()
4012 status = write16(state, OFDM_SC_COMM_STATE__A, 0); in set_dvbt()
4015 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); in set_dvbt()
4020 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt()
4032 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, in set_dvbt()
4037 if (!state->m_drxk_a3_rom_code) in set_dvbt()
4038 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); in set_dvbt()
4056 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_dvbt_lock_status() argument
4072 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); in get_dvbt_lock_status()
4078 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); in get_dvbt_lock_status()
4097 static int power_up_qam(struct drxk_state *state) in power_up_qam() argument
4103 status = ctrl_power_mode(state, &power_mode); in power_up_qam()
4112 static int power_down_qam(struct drxk_state *state) in power_down_qam() argument
4119 status = read16(state, SCU_COMM_EXEC__A, &data); in power_down_qam()
4128 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in power_down_qam()
4131 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in power_down_qam()
4138 status = set_iqm_af(state, false); in power_down_qam()
4160 static int set_qam_measurement(struct drxk_state *state, in set_qam_measurement() argument
4221 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); in set_qam_measurement()
4224 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, in set_qam_measurement()
4228 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); in set_qam_measurement()
4235 static int set_qam16(struct drxk_state *state) in set_qam16() argument
4242 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); in set_qam16()
4245 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); in set_qam16()
4248 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); in set_qam16()
4251 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); in set_qam16()
4254 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); in set_qam16()
4257 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); in set_qam16()
4261 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); in set_qam16()
4264 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); in set_qam16()
4267 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); in set_qam16()
4270 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); in set_qam16()
4273 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); in set_qam16()
4276 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam16()
4280 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam16()
4283 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam16()
4286 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam16()
4291 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam16()
4297 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam16()
4300 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam16()
4303 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam16()
4306 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam16()
4309 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam16()
4312 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam16()
4315 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam16()
4318 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam16()
4322 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam16()
4325 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in set_qam16()
4328 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in set_qam16()
4331 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam16()
4334 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in set_qam16()
4337 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam16()
4340 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam16()
4343 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in set_qam16()
4346 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); in set_qam16()
4349 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam16()
4352 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam16()
4355 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam16()
4362 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); in set_qam16()
4365 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in set_qam16()
4368 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); in set_qam16()
4371 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); in set_qam16()
4374 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); in set_qam16()
4377 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); in set_qam16()
4381 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam16()
4384 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam16()
4387 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); in set_qam16()
4394 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); in set_qam16()
4397 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); in set_qam16()
4400 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); in set_qam16()
4403 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); in set_qam16()
4406 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in set_qam16()
4409 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in set_qam16()
4412 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in set_qam16()
4429 static int set_qam32(struct drxk_state *state) in set_qam32() argument
4437 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); in set_qam32()
4440 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); in set_qam32()
4443 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); in set_qam32()
4446 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); in set_qam32()
4449 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); in set_qam32()
4452 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); in set_qam32()
4457 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); in set_qam32()
4460 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); in set_qam32()
4463 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); in set_qam32()
4466 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); in set_qam32()
4469 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in set_qam32()
4472 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam32()
4476 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in set_qam32()
4479 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in set_qam32()
4482 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam32()
4488 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam32()
4496 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam32()
4499 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam32()
4502 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam32()
4505 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam32()
4508 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam32()
4511 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam32()
4514 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam32()
4517 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam32()
4521 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam32()
4524 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in set_qam32()
4527 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in set_qam32()
4530 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam32()
4533 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in set_qam32()
4536 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam32()
4539 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam32()
4542 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in set_qam32()
4545 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); in set_qam32()
4548 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam32()
4551 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam32()
4554 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in set_qam32()
4561 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); in set_qam32()
4564 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in set_qam32()
4567 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam32()
4570 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam32()
4573 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); in set_qam32()
4576 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in set_qam32()
4580 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam32()
4583 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam32()
4586 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); in set_qam32()
4593 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in set_qam32()
4596 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); in set_qam32()
4599 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in set_qam32()
4602 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in set_qam32()
4605 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in set_qam32()
4608 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in set_qam32()
4611 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in set_qam32()
4625 static int set_qam64(struct drxk_state *state) in set_qam64() argument
4632 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); in set_qam64()
4635 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); in set_qam64()
4638 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); in set_qam64()
4641 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); in set_qam64()
4644 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); in set_qam64()
4647 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); in set_qam64()
4652 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); in set_qam64()
4655 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); in set_qam64()
4658 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); in set_qam64()
4661 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); in set_qam64()
4664 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in set_qam64()
4667 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam64()
4671 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam64()
4674 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam64()
4677 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam64()
4682 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam64()
4690 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam64()
4693 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam64()
4696 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam64()
4699 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam64()
4702 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam64()
4705 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam64()
4708 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam64()
4711 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam64()
4715 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam64()
4718 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); in set_qam64()
4721 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); in set_qam64()
4724 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam64()
4727 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); in set_qam64()
4730 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam64()
4733 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam64()
4736 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam64()
4739 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in set_qam64()
4742 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam64()
4745 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam64()
4748 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam64()
4755 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); in set_qam64()
4758 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam64()
4761 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam64()
4764 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); in set_qam64()
4767 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); in set_qam64()
4770 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); in set_qam64()
4774 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam64()
4777 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam64()
4780 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); in set_qam64()
4787 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in set_qam64()
4790 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); in set_qam64()
4793 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); in set_qam64()
4796 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); in set_qam64()
4799 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in set_qam64()
4802 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in set_qam64()
4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in set_qam64()
4820 static int set_qam128(struct drxk_state *state) in set_qam128() argument
4827 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); in set_qam128()
4830 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); in set_qam128()
4833 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); in set_qam128()
4836 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); in set_qam128()
4839 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); in set_qam128()
4842 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); in set_qam128()
4847 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); in set_qam128()
4850 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); in set_qam128()
4853 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); in set_qam128()
4856 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); in set_qam128()
4859 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); in set_qam128()
4862 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam128()
4866 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in set_qam128()
4869 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in set_qam128()
4872 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam128()
4879 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam128()
4887 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam128()
4890 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam128()
4893 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam128()
4896 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam128()
4899 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam128()
4902 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam128()
4905 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam128()
4908 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam128()
4912 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam128()
4915 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); in set_qam128()
4918 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); in set_qam128()
4921 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam128()
4924 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); in set_qam128()
4927 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); in set_qam128()
4930 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam128()
4933 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam128()
4936 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); in set_qam128()
4939 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam128()
4942 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam128()
4945 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in set_qam128()
4952 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in set_qam128()
4955 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam128()
4958 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam128()
4961 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam128()
4964 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); in set_qam128()
4967 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in set_qam128()
4971 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam128()
4974 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); in set_qam128()
4978 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in set_qam128()
4984 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in set_qam128()
4987 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); in set_qam128()
4990 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); in set_qam128()
4993 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); in set_qam128()
4996 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in set_qam128()
4999 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in set_qam128()
5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in set_qam128()
5017 static int set_qam256(struct drxk_state *state) in set_qam256() argument
5024 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); in set_qam256()
5027 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); in set_qam256()
5030 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); in set_qam256()
5033 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); in set_qam256()
5036 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); in set_qam256()
5039 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); in set_qam256()
5044 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); in set_qam256()
5047 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); in set_qam256()
5050 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); in set_qam256()
5053 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); in set_qam256()
5056 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); in set_qam256()
5059 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam256()
5063 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam256()
5066 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam256()
5069 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam256()
5075 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam256()
5083 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam256()
5086 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam256()
5089 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam256()
5092 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam256()
5095 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam256()
5098 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam256()
5101 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam256()
5104 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam256()
5108 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam256()
5111 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); in set_qam256()
5114 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); in set_qam256()
5117 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam256()
5120 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); in set_qam256()
5123 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); in set_qam256()
5126 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam256()
5129 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam256()
5132 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in set_qam256()
5135 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam256()
5138 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam256()
5141 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam256()
5148 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in set_qam256()
5151 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam256()
5154 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam256()
5157 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam256()
5160 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); in set_qam256()
5163 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); in set_qam256()
5167 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam256()
5170 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam256()
5173 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in set_qam256()
5180 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in set_qam256()
5183 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); in set_qam256()
5186 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); in set_qam256()
5189 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); in set_qam256()
5192 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); in set_qam256()
5195 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); in set_qam256()
5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in set_qam256()
5213 static int qam_reset_qam(struct drxk_state *state) in qam_reset_qam() argument
5220 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in qam_reset_qam()
5224 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in qam_reset_qam()
5241 static int qam_set_symbolrate(struct drxk_state *state) in qam_set_symbolrate() argument
5252 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; in qam_set_symbolrate()
5254 if (state->props.symbol_rate <= 1188750) in qam_set_symbolrate()
5256 else if (state->props.symbol_rate <= 2377500) in qam_set_symbolrate()
5258 else if (state->props.symbol_rate <= 4755000) in qam_set_symbolrate()
5260 status = write16(state, IQM_FD_RATESEL__A, ratesel); in qam_set_symbolrate()
5267 symb_freq = state->props.symbol_rate * (1 << ratesel); in qam_set_symbolrate()
5276 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); in qam_set_symbolrate()
5279 state->m_iqm_rc_rate = iqm_rc_rate; in qam_set_symbolrate()
5283 symb_freq = state->props.symbol_rate; in qam_set_symbolrate()
5294 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); in qam_set_symbolrate()
5311 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_qam_lock_status() argument
5318 status = scu_command(state, in get_qam_lock_status()
5352 static int qam_demodulator_command(struct drxk_state *state, in qam_demodulator_command() argument
5359 set_param_parameters[0] = state->m_constellation; /* modulation */ in qam_demodulator_command()
5365 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5370 status = scu_command(state, in qam_demodulator_command()
5377 status = scu_command(state, in qam_demodulator_command()
5383 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5393 status = scu_command(state, in qam_demodulator_command()
5410 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, in set_qam() argument
5415 int qam_demod_param_count = state->qam_demod_parameter_count; in set_qam()
5424 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); in set_qam()
5427 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); in set_qam()
5430 status = qam_reset_qam(state); in set_qam()
5439 status = qam_set_symbolrate(state); in set_qam()
5444 switch (state->props.modulation) { in set_qam()
5446 state->m_constellation = DRX_CONSTELLATION_QAM256; in set_qam()
5450 state->m_constellation = DRX_CONSTELLATION_QAM64; in set_qam()
5453 state->m_constellation = DRX_CONSTELLATION_QAM16; in set_qam()
5456 state->m_constellation = DRX_CONSTELLATION_QAM32; in set_qam()
5459 state->m_constellation = DRX_CONSTELLATION_QAM128; in set_qam()
5470 if (state->qam_demod_parameter_count == 4 in set_qam()
5471 || !state->qam_demod_parameter_count) { in set_qam()
5473 status = qam_demodulator_command(state, qam_demod_param_count); in set_qam()
5479 if (state->qam_demod_parameter_count == 2 in set_qam()
5480 || (!state->qam_demod_parameter_count && status < 0)) { in set_qam()
5482 status = qam_demodulator_command(state, qam_demod_param_count); in set_qam()
5489 state->qam_demod_parameter_count, in set_qam()
5490 state->microcode_name); in set_qam()
5492 } else if (!state->qam_demod_parameter_count) { in set_qam()
5501 state->qam_demod_parameter_count = qam_demod_param_count; in set_qam()
5513 status = set_frequency_shifter(state, intermediate_freqk_hz, in set_qam()
5519 status = set_qam_measurement(state, state->m_constellation, in set_qam()
5520 state->props.symbol_rate); in set_qam()
5525 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); in set_qam()
5528 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); in set_qam()
5533 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); in set_qam()
5536 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); in set_qam()
5539 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); in set_qam()
5542 status = write16(state, QAM_LC_MODE__A, 7); in set_qam()
5546 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); in set_qam()
5549 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); in set_qam()
5552 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); in set_qam()
5555 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); in set_qam()
5558 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); in set_qam()
5561 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); in set_qam()
5564 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); in set_qam()
5567 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); in set_qam()
5570 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); in set_qam()
5573 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); in set_qam()
5576 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); in set_qam()
5579 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); in set_qam()
5582 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); in set_qam()
5585 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); in set_qam()
5588 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); in set_qam()
5593 status = write16(state, QAM_SY_SP_INV__A, in set_qam()
5599 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_qam()
5604 switch (state->props.modulation) { in set_qam()
5606 status = set_qam16(state); in set_qam()
5609 status = set_qam32(state); in set_qam()
5613 status = set_qam64(state); in set_qam()
5616 status = set_qam128(state); in set_qam()
5619 status = set_qam256(state); in set_qam()
5629 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_qam()
5636 status = mpegts_dto_setup(state, state->m_operation_mode); in set_qam()
5641 status = mpegts_start(state); in set_qam()
5644 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in set_qam()
5647 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); in set_qam()
5650 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in set_qam()
5655 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in set_qam()
5670 static int set_qam_standard(struct drxk_state *state, in set_qam_standard() argument
5683 switch_antenna_to_qam(state); in set_qam_standard()
5686 status = power_up_qam(state); in set_qam_standard()
5690 status = qam_reset_qam(state); in set_qam_standard()
5696 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in set_qam_standard()
5699 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in set_qam_standard()
5707 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, in set_qam_standard()
5712 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, in set_qam_standard()
5718 status = bl_direct_cmd(state, in set_qam_standard()
5730 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); in set_qam_standard()
5733 status = write16(state, IQM_CF_SYMMETRIC__A, 0); in set_qam_standard()
5736 status = write16(state, IQM_CF_MIDTAP__A, in set_qam_standard()
5741 status = write16(state, IQM_RC_STRETCH__A, 21); in set_qam_standard()
5744 status = write16(state, IQM_AF_CLP_LEN__A, 0); in set_qam_standard()
5747 status = write16(state, IQM_AF_CLP_TH__A, 448); in set_qam_standard()
5750 status = write16(state, IQM_AF_SNS_LEN__A, 0); in set_qam_standard()
5753 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); in set_qam_standard()
5757 status = write16(state, IQM_FS_ADJ_SEL__A, 1); in set_qam_standard()
5760 status = write16(state, IQM_RC_ADJ_SEL__A, 1); in set_qam_standard()
5763 status = write16(state, IQM_CF_ADJ_SEL__A, 1); in set_qam_standard()
5766 status = write16(state, IQM_AF_UPD_SEL__A, 0); in set_qam_standard()
5771 status = write16(state, IQM_CF_CLP_VAL__A, 500); in set_qam_standard()
5774 status = write16(state, IQM_CF_DATATH__A, 1000); in set_qam_standard()
5777 status = write16(state, IQM_CF_BYPASSDET__A, 1); in set_qam_standard()
5780 status = write16(state, IQM_CF_DET_LCT__A, 0); in set_qam_standard()
5783 status = write16(state, IQM_CF_WND_LEN__A, 1); in set_qam_standard()
5786 status = write16(state, IQM_CF_PKDTH__A, 1); in set_qam_standard()
5789 status = write16(state, IQM_AF_INC_BYPASS__A, 1); in set_qam_standard()
5794 status = set_iqm_af(state, true); in set_qam_standard()
5797 status = write16(state, IQM_AF_START_LOCK__A, 0x01); in set_qam_standard()
5802 status = adc_synchronization(state); in set_qam_standard()
5807 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); in set_qam_standard()
5812 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_qam_standard()
5819 status = init_agc(state, true); in set_qam_standard()
5822 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); in set_qam_standard()
5827 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); in set_qam_standard()
5830 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); in set_qam_standard()
5835 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_qam_standard()
5842 static int write_gpio(struct drxk_state *state) in write_gpio() argument
5849 status = write16(state, SCU_RAM_GPIO__A, in write_gpio()
5855 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in write_gpio()
5859 if (state->m_has_sawsw) { in write_gpio()
5860 if (state->uio_mask & 0x0001) { /* UIO-1 */ in write_gpio()
5862 status = write16(state, SIO_PDR_SMA_TX_CFG__A, in write_gpio()
5863 state->m_gpio_cfg); in write_gpio()
5868 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5871 if ((state->m_gpio & 0x0001) == 0) in write_gpio()
5876 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5880 if (state->uio_mask & 0x0002) { /* UIO-2 */ in write_gpio()
5882 status = write16(state, SIO_PDR_SMA_RX_CFG__A, in write_gpio()
5883 state->m_gpio_cfg); in write_gpio()
5888 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5891 if ((state->m_gpio & 0x0002) == 0) in write_gpio()
5896 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5900 if (state->uio_mask & 0x0004) { /* UIO-3 */ in write_gpio()
5902 status = write16(state, SIO_PDR_GPIO_CFG__A, in write_gpio()
5903 state->m_gpio_cfg); in write_gpio()
5908 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5911 if ((state->m_gpio & 0x0004) == 0) in write_gpio()
5916 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5922 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in write_gpio()
5929 static int switch_antenna_to_qam(struct drxk_state *state) in switch_antenna_to_qam() argument
5936 if (!state->antenna_gpio) in switch_antenna_to_qam()
5939 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_qam()
5941 if (state->antenna_dvbt ^ gpio_state) { in switch_antenna_to_qam()
5943 if (state->antenna_dvbt) in switch_antenna_to_qam()
5944 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_qam()
5946 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_qam()
5947 status = write_gpio(state); in switch_antenna_to_qam()
5954 static int switch_antenna_to_dvbt(struct drxk_state *state) in switch_antenna_to_dvbt() argument
5961 if (!state->antenna_gpio) in switch_antenna_to_dvbt()
5964 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_dvbt()
5966 if (!(state->antenna_dvbt ^ gpio_state)) { in switch_antenna_to_dvbt()
5968 if (state->antenna_dvbt) in switch_antenna_to_dvbt()
5969 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_dvbt()
5971 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_dvbt()
5972 status = write_gpio(state); in switch_antenna_to_dvbt()
5980 static int power_down_device(struct drxk_state *state) in power_down_device() argument
5991 if (state->m_b_p_down_open_bridge) { in power_down_device()
5993 status = ConfigureI2CBridge(state, true); in power_down_device()
5998 status = dvbt_enable_ofdm_token_ring(state, false); in power_down_device()
6002 status = write16(state, SIO_CC_PWD_MODE__A, in power_down_device()
6006 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in power_down_device()
6009 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in power_down_device()
6010 status = hi_cfg_command(state); in power_down_device()
6018 static int init_drxk(struct drxk_state *state) in init_drxk() argument
6025 if (state->m_drxk_state == DRXK_UNINITIALIZED) { in init_drxk()
6026 drxk_i2c_lock(state); in init_drxk()
6027 status = power_up_device(state); in init_drxk()
6030 status = drxx_open(state); in init_drxk()
6034 status = write16(state, SIO_CC_SOFT_RST__A, in init_drxk()
6040 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in init_drxk()
6048 state->m_drxk_a3_patch_code = true; in init_drxk()
6049 status = get_device_capabilities(state); in init_drxk()
6056 state->m_hi_cfg_bridge_delay = in init_drxk()
6057 (u16) ((state->m_osc_clock_freq / 1000) * in init_drxk()
6060 if (state->m_hi_cfg_bridge_delay > in init_drxk()
6062 state->m_hi_cfg_bridge_delay = in init_drxk()
6066 state->m_hi_cfg_bridge_delay += in init_drxk()
6067 state->m_hi_cfg_bridge_delay << in init_drxk()
6070 status = init_hi(state); in init_drxk()
6075 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6076 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6079 status = write16(state, SCU_RAM_GPIO__A, in init_drxk()
6086 status = mpegts_disable(state); in init_drxk()
6091 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); in init_drxk()
6094 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); in init_drxk()
6099 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, in init_drxk()
6105 status = write16(state, SIO_BL_COMM_EXEC__A, in init_drxk()
6109 status = bl_chain_cmd(state, 0, 6, 100); in init_drxk()
6113 if (state->fw) { in init_drxk()
6114 status = download_microcode(state, state->fw->data, in init_drxk()
6115 state->fw->size); in init_drxk()
6121 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, in init_drxk()
6127 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in init_drxk()
6130 status = drxx_open(state); in init_drxk()
6137 status = ctrl_power_mode(state, &power_mode); in init_drxk()
6152 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, in init_drxk()
6161 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, in init_drxk()
6181 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); in init_drxk()
6187 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); in init_drxk()
6191 status = mpegts_dto_init(state); in init_drxk()
6194 status = mpegts_stop(state); in init_drxk()
6197 status = mpegts_configure_polarity(state); in init_drxk()
6200 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); in init_drxk()
6204 status = write_gpio(state); in init_drxk()
6208 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6210 if (state->m_b_power_down) { in init_drxk()
6211 status = power_down_device(state); in init_drxk()
6214 state->m_drxk_state = DRXK_POWERED_DOWN; in init_drxk()
6216 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6220 if (state->m_has_dvbc) { in init_drxk()
6221 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in init_drxk()
6222 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in init_drxk()
6223 strlcat(state->frontend.ops.info.name, " DVB-C", in init_drxk()
6224 sizeof(state->frontend.ops.info.name)); in init_drxk()
6226 if (state->m_has_dvbt) { in init_drxk()
6227 state->frontend.ops.delsys[n++] = SYS_DVBT; in init_drxk()
6228 strlcat(state->frontend.ops.info.name, " DVB-T", in init_drxk()
6229 sizeof(state->frontend.ops.info.name)); in init_drxk()
6231 drxk_i2c_unlock(state); in init_drxk()
6235 state->m_drxk_state = DRXK_NO_DEV; in init_drxk()
6236 drxk_i2c_unlock(state); in init_drxk()
6246 struct drxk_state *state = context; in load_firmware_cb() local
6251 state->microcode_name); in load_firmware_cb()
6253 state->microcode_name); in load_firmware_cb()
6254 state->microcode_name = NULL; in load_firmware_cb()
6267 state->fw = fw; in load_firmware_cb()
6269 init_drxk(state); in load_firmware_cb()
6274 struct drxk_state *state = fe->demodulator_priv; in drxk_release() local
6277 release_firmware(state->fw); in drxk_release()
6279 kfree(state); in drxk_release()
6284 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep() local
6288 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_sleep()
6290 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_sleep()
6293 shut_down(state); in drxk_sleep()
6299 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl() local
6303 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_gate_ctrl()
6306 return ConfigureI2CBridge(state, enable ? true : false); in drxk_gate_ctrl()
6313 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters() local
6318 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_set_parameters()
6321 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_set_parameters()
6336 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6337 state->props = *p; in drxk_set_parameters()
6340 shut_down(state); in drxk_set_parameters()
6344 if (!state->m_has_dvbc) in drxk_set_parameters()
6346 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? in drxk_set_parameters()
6348 if (state->m_itut_annex_c) in drxk_set_parameters()
6349 setoperation_mode(state, OM_QAM_ITU_C); in drxk_set_parameters()
6351 setoperation_mode(state, OM_QAM_ITU_A); in drxk_set_parameters()
6354 if (!state->m_has_dvbt) in drxk_set_parameters()
6356 setoperation_mode(state, OM_DVBT); in drxk_set_parameters()
6364 start(state, 0, IF); in drxk_set_parameters()
6381 static int get_strength(struct drxk_state *state, u64 *strength) in get_strength() argument
6396 if (is_dvbt(state)) { in get_strength()
6397 rf_agc = state->m_dvbt_rf_agc_cfg; in get_strength()
6398 if_agc = state->m_dvbt_if_agc_cfg; in get_strength()
6399 } else if (is_qam(state)) { in get_strength()
6400 rf_agc = state->m_qam_rf_agc_cfg; in get_strength()
6401 if_agc = state->m_qam_if_agc_cfg; in get_strength()
6403 rf_agc = state->m_atv_rf_agc_cfg; in get_strength()
6404 if_agc = state->m_atv_if_agc_cfg; in get_strength()
6409 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); in get_strength()
6414 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); in get_strength()
6442 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, in get_strength()
6447 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, in get_strength()
6485 struct drxk_state *state = fe->demodulator_priv; in drxk_get_stats() local
6498 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_stats()
6500 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_stats()
6504 state->fe_status = 0; in drxk_get_stats()
6505 get_lock_status(state, &stat); in drxk_get_stats()
6507 state->fe_status |= 0x1f; in drxk_get_stats()
6509 state->fe_status |= 0x0f; in drxk_get_stats()
6511 state->fe_status |= 0x07; in drxk_get_stats()
6516 get_strength(state, &c->strength.stat[0].uvalue); in drxk_get_stats()
6521 get_signal_to_noise(state, &cnr); in drxk_get_stats()
6549 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); in drxk_get_stats()
6554 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); in drxk_get_stats()
6560 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); in drxk_get_stats()
6565 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); in drxk_get_stats()
6570 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); in drxk_get_stats()
6575 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); in drxk_get_stats()
6579 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in drxk_get_stats()
6608 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status() local
6617 *status = state->fe_status; in drxk_read_status()
6625 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength() local
6630 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_signal_strength()
6632 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_signal_strength()
6641 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr() local
6646 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_snr()
6648 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_snr()
6651 get_signal_to_noise(state, &snr2); in drxk_read_snr()
6662 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks() local
6667 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_ucblocks()
6669 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_ucblocks()
6672 dvbtqam_get_acc_pkt_err(state, &err); in drxk_read_ucblocks()
6680 struct drxk_state *state = fe->demodulator_priv; in drxk_get_tune_settings() local
6685 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_tune_settings()
6687 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_tune_settings()
6740 struct drxk_state *state = NULL; in drxk_attach() local
6745 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); in drxk_attach()
6746 if (!state) in drxk_attach()
6749 state->i2c = i2c; in drxk_attach()
6750 state->demod_address = adr; in drxk_attach()
6751 state->single_master = config->single_master; in drxk_attach()
6752 state->microcode_name = config->microcode_name; in drxk_attach()
6753 state->qam_demod_parameter_count = config->qam_demod_parameter_count; in drxk_attach()
6754 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6755 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6756 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6757 state->m_chunk_size = config->chunk_size; in drxk_attach()
6758 state->enable_merr_cfg = config->enable_merr_cfg; in drxk_attach()
6761 state->m_dvbt_static_clk = false; in drxk_attach()
6762 state->m_dvbc_static_clk = false; in drxk_attach()
6764 state->m_dvbt_static_clk = true; in drxk_attach()
6765 state->m_dvbc_static_clk = true; in drxk_attach()
6770 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; in drxk_attach()
6772 state->m_ts_clockk_strength = 0x06; in drxk_attach()
6775 state->m_enable_parallel = true; in drxk_attach()
6777 state->m_enable_parallel = false; in drxk_attach()
6780 state->uio_mask = config->antenna_gpio; in drxk_attach()
6783 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6784 state->m_gpio |= state->antenna_gpio; in drxk_attach()
6786 state->m_gpio &= ~state->antenna_gpio; in drxk_attach()
6788 mutex_init(&state->mutex); in drxk_attach()
6790 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6791 state->frontend.demodulator_priv = state; in drxk_attach()
6793 init_state(state); in drxk_attach()
6796 if (state->microcode_name) { in drxk_attach()
6799 status = request_firmware(&fw, state->microcode_name, in drxk_attach()
6800 state->i2c->dev.parent); in drxk_attach()
6803 load_firmware_cb(fw, state); in drxk_attach()
6804 } else if (init_drxk(state) < 0) in drxk_attach()
6809 p = &state->frontend.dtv_property_cache; in drxk_attach()
6829 return &state->frontend; in drxk_attach()
6833 kfree(state); in drxk_attach()