Lines Matching refs:state
200 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) in dib0090_read_reg() argument
204 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_read_reg()
209 state->i2c_write_buffer[0] = reg; in dib0090_read_reg()
211 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib0090_read_reg()
212 state->msg[0].addr = state->config->i2c_address; in dib0090_read_reg()
213 state->msg[0].flags = 0; in dib0090_read_reg()
214 state->msg[0].buf = state->i2c_write_buffer; in dib0090_read_reg()
215 state->msg[0].len = 1; in dib0090_read_reg()
216 state->msg[1].addr = state->config->i2c_address; in dib0090_read_reg()
217 state->msg[1].flags = I2C_M_RD; in dib0090_read_reg()
218 state->msg[1].buf = state->i2c_read_buffer; in dib0090_read_reg()
219 state->msg[1].len = 2; in dib0090_read_reg()
221 if (i2c_transfer(state->i2c, state->msg, 2) != 2) { in dib0090_read_reg()
225 ret = (state->i2c_read_buffer[0] << 8) in dib0090_read_reg()
226 | state->i2c_read_buffer[1]; in dib0090_read_reg()
228 mutex_unlock(&state->i2c_buffer_lock); in dib0090_read_reg()
232 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) in dib0090_write_reg() argument
236 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_write_reg()
241 state->i2c_write_buffer[0] = reg & 0xff; in dib0090_write_reg()
242 state->i2c_write_buffer[1] = val >> 8; in dib0090_write_reg()
243 state->i2c_write_buffer[2] = val & 0xff; in dib0090_write_reg()
245 memset(state->msg, 0, sizeof(struct i2c_msg)); in dib0090_write_reg()
246 state->msg[0].addr = state->config->i2c_address; in dib0090_write_reg()
247 state->msg[0].flags = 0; in dib0090_write_reg()
248 state->msg[0].buf = state->i2c_write_buffer; in dib0090_write_reg()
249 state->msg[0].len = 3; in dib0090_write_reg()
251 if (i2c_transfer(state->i2c, state->msg, 1) != 1) { in dib0090_write_reg()
257 mutex_unlock(&state->i2c_buffer_lock); in dib0090_write_reg()
261 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg) in dib0090_fw_read_reg() argument
265 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_read_reg()
270 state->i2c_write_buffer[0] = reg; in dib0090_fw_read_reg()
272 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_read_reg()
273 state->msg.addr = reg; in dib0090_fw_read_reg()
274 state->msg.flags = I2C_M_RD; in dib0090_fw_read_reg()
275 state->msg.buf = state->i2c_read_buffer; in dib0090_fw_read_reg()
276 state->msg.len = 2; in dib0090_fw_read_reg()
277 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { in dib0090_fw_read_reg()
281 ret = (state->i2c_read_buffer[0] << 8) in dib0090_fw_read_reg()
282 | state->i2c_read_buffer[1]; in dib0090_fw_read_reg()
284 mutex_unlock(&state->i2c_buffer_lock); in dib0090_fw_read_reg()
288 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) in dib0090_fw_write_reg() argument
292 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_write_reg()
297 state->i2c_write_buffer[0] = val >> 8; in dib0090_fw_write_reg()
298 state->i2c_write_buffer[1] = val & 0xff; in dib0090_fw_write_reg()
300 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_write_reg()
301 state->msg.addr = reg; in dib0090_fw_write_reg()
302 state->msg.flags = 0; in dib0090_fw_write_reg()
303 state->msg.buf = state->i2c_write_buffer; in dib0090_fw_write_reg()
304 state->msg.len = 2; in dib0090_fw_write_reg()
305 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { in dib0090_fw_write_reg()
311 mutex_unlock(&state->i2c_buffer_lock); in dib0090_fw_write_reg()
315 #define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); … argument
320 static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c) in dib0090_write_regs() argument
323 dib0090_write_reg(state, r++, *b++); in dib0090_write_regs()
329 struct dib0090_state *state = fe->tuner_priv; in dib0090_identify() local
331 struct dib0090_identity *identity = &state->identity; in dib0090_identify()
333 v = dib0090_read_reg(state, 0x1a); in dib0090_identify()
421 struct dib0090_fw_state *state = fe->tuner_priv; in dib0090_fw_identify() local
422 struct dib0090_identity *identity = &state->identity; in dib0090_fw_identify()
424 u16 v = dib0090_fw_read_reg(state, 0x1a); in dib0090_fw_identify()
511 struct dib0090_state *state = fe->tuner_priv; in dib0090_reset_digital() local
514 HARD_RESET(state); in dib0090_reset_digital()
515 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_reset_digital()
519 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remai… in dib0090_reset_digital()
521 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <… in dib0090_reset_digital()
523 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
526 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
530 PllCfg = dib0090_read_reg(state, 0x21); in dib0090_reset_digital()
538 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
542 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
546 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
550 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
555 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); in dib0090_reset_digital()
567 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
572 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
578 struct dib0090_fw_state *state = fe->tuner_priv; in dib0090_fw_reset_digital() local
584 HARD_RESET(state); in dib0090_fw_reset_digital()
586 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_fw_reset_digital()
587 …dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL re… in dib0090_fw_reset_digital()
589 dib0090_fw_write_reg(state, 0x20, in dib0090_fw_reset_digital()
599 dib0090_fw_write_reg(state, 0x23, v); in dib0090_fw_reset_digital()
602 PllCfg = dib0090_fw_read_reg(state, 0x21); in dib0090_fw_reset_digital()
609 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
613 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
617 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
621 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
626 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800); in dib0090_fw_reset_digital()
638 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
643 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
651 struct dib0090_state *state = fe->tuner_priv; in dib0090_wakeup() local
652 if (state->config->sleep) in dib0090_wakeup()
653 state->config->sleep(fe, 0); in dib0090_wakeup()
656 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_wakeup()
662 struct dib0090_state *state = fe->tuner_priv; in dib0090_sleep() local
663 if (state->config->sleep) in dib0090_sleep()
664 state->config->sleep(fe, 1); in dib0090_sleep()
670 struct dib0090_state *state = fe->tuner_priv; in dib0090_dcc_freq() local
672 dib0090_write_reg(state, 0x04, 0); in dib0090_dcc_freq()
674 dib0090_write_reg(state, 0x04, 1); in dib0090_dcc_freq()
882 static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd) in dib0090_wbd_to_db() argument
885 if (wbd < state->wbd_offset) in dib0090_wbd_to_db()
888 wbd -= state->wbd_offset; in dib0090_wbd_to_db()
893 static void dib0090_wbd_target(struct dib0090_state *state, u32 rf) in dib0090_wbd_target() argument
899 if (state->current_band == BAND_VHF) in dib0090_wbd_target()
902 if (state->current_band == BAND_VHF) in dib0090_wbd_target()
903 offset = state->config->wbd_vhf_offset; in dib0090_wbd_target()
904 if (state->current_band == BAND_CBAND) in dib0090_wbd_target()
905 offset = state->config->wbd_cband_offset; in dib0090_wbd_target()
908 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset); in dib0090_wbd_target()
909 dprintk("wbd-target: %d dB\n", (u32) state->wbd_target); in dib0090_wbd_target()
916 static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force) in dib0090_gain_apply() argument
932 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */ in dib0090_gain_apply()
933 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_apply()
935 state->rf_gain_limit += top_delta; in dib0090_gain_apply()
937 if (state->rf_gain_limit < 0) /*underflow */ in dib0090_gain_apply()
938 state->rf_gain_limit = 0; in dib0090_gain_apply()
941 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA; in dib0090_gain_apply()
942 if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */ in dib0090_gain_apply()
943 state->current_gain = gain; in dib0090_gain_apply()
945 state->current_gain += gain_delta; in dib0090_gain_apply()
947 if (state->current_gain < 0) in dib0090_gain_apply()
948 state->current_gain = 0; in dib0090_gain_apply()
951 gain = state->current_gain >> GAIN_ALPHA; in dib0090_gain_apply()
954 if (gain > (state->rf_gain_limit >> WBD_ALPHA)) { in dib0090_gain_apply()
955 rf = state->rf_gain_limit >> WBD_ALPHA; in dib0090_gain_apply()
957 if (bb > state->bb_ramp[0]) in dib0090_gain_apply()
958 bb = state->bb_ramp[0]; in dib0090_gain_apply()
964 state->gain[0] = rf; in dib0090_gain_apply()
965 state->gain[1] = bb; in dib0090_gain_apply()
969 g = state->rf_ramp + 1; /* point on RF LNA1 max gain */ in dib0090_gain_apply()
988 gain_reg[2] = v | state->rf_lt_def; in dib0090_gain_apply()
998 g = state->bb_ramp + 1; /* point on BB gain 1 max gain */ in dib0090_gain_apply()
1002 gain_reg[3] |= state->bb_1_def; in dib0090_gain_apply()
1013 if (force || state->gain_reg[i] != v) { in dib0090_gain_apply()
1014 state->gain_reg[i] = v; in dib0090_gain_apply()
1015 dib0090_write_reg(state, gain_reg_addr[i], v); in dib0090_gain_apply()
1020 static void dib0090_set_boost(struct dib0090_state *state, int onoff) in dib0090_set_boost() argument
1022 state->bb_1_def &= 0xdfff; in dib0090_set_boost()
1023 state->bb_1_def |= onoff << 13; in dib0090_set_boost()
1026 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg) in dib0090_set_rframp() argument
1028 state->rf_ramp = cfg; in dib0090_set_rframp()
1031 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg) in dib0090_set_rframp_pwm() argument
1033 state->rf_ramp = cfg; in dib0090_set_rframp_pwm()
1035 dib0090_write_reg(state, 0x2a, 0xffff); in dib0090_set_rframp_pwm()
1037 dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); in dib0090_set_rframp_pwm()
1039 dib0090_write_regs(state, 0x2c, cfg + 3, 6); in dib0090_set_rframp_pwm()
1040 dib0090_write_regs(state, 0x3e, cfg + 9, 2); in dib0090_set_rframp_pwm()
1043 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg) in dib0090_set_bbramp() argument
1045 state->bb_ramp = cfg; in dib0090_set_bbramp()
1046 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp()
1049 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg) in dib0090_set_bbramp_pwm() argument
1051 state->bb_ramp = cfg; in dib0090_set_bbramp_pwm()
1053 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp_pwm()
1055 dib0090_write_reg(state, 0x33, 0xffff); in dib0090_set_bbramp_pwm()
1056 dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33)); in dib0090_set_bbramp_pwm()
1057 dib0090_write_regs(state, 0x35, cfg + 3, 4); in dib0090_set_bbramp_pwm()
1062 struct dib0090_state *state = fe->tuner_priv; in dib0090_pwm_gain_reset() local
1068 if (state->config->use_pwm_agc) { in dib0090_pwm_gain_reset()
1069 if (state->current_band == BAND_CBAND) { in dib0090_pwm_gain_reset()
1070 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1072 … if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_pwm_gain_reset()
1074 …else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_2… in dib0090_pwm_gain_reset()
1075 if (state->config->is_dib7090e) { in dib0090_pwm_gain_reset()
1076 if (state->rf_ramp == NULL) in dib0090_pwm_gain_reset()
1079 rf_ramp = state->rf_ramp; in dib0090_pwm_gain_reset()
1087 if (state->current_band == BAND_VHF) { in dib0090_pwm_gain_reset()
1088 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1093 } else if (state->current_band == BAND_UHF) { in dib0090_pwm_gain_reset()
1094 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1096 … if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_pwm_gain_reset()
1098 …else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_2… in dib0090_pwm_gain_reset()
1104 dib0090_set_rframp_pwm(state, rf_ramp); in dib0090_pwm_gain_reset()
1105 dib0090_set_bbramp_pwm(state, bb_ramp); in dib0090_pwm_gain_reset()
1108 if (state->rf_ramp) in dib0090_pwm_gain_reset()
1110 state->rf_ramp[0], in dib0090_pwm_gain_reset()
1111 (state->current_band == BAND_CBAND) ? "CBAND" : "NOT CBAND", in dib0090_pwm_gain_reset()
1112 state->identity.version & 0x1f); in dib0090_pwm_gain_reset()
1114 if (rf_ramp && ((state->rf_ramp && state->rf_ramp[0] == 0) || in dib0090_pwm_gain_reset()
1115 (state->current_band == BAND_CBAND && in dib0090_pwm_gain_reset()
1116 (state->identity.version & 0x1f) <= P1D_E_F))) { in dib0090_pwm_gain_reset()
1122 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); in dib0090_pwm_gain_reset()
1125 if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) in dib0090_pwm_gain_reset()
1126 dib0090_write_reg(state, 0x04, 3); in dib0090_pwm_gain_reset()
1128 dib0090_write_reg(state, 0x04, 1); in dib0090_pwm_gain_reset()
1129 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ in dib0090_pwm_gain_reset()
1136 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_dc_servo() local
1138 dib0090_write_reg(state, 0x04, DC_servo_cutoff); in dib0090_set_dc_servo()
1142 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state) in dib0090_get_slow_adc_val() argument
1144 u16 adc_val = dib0090_read_reg(state, 0x1d); in dib0090_get_slow_adc_val()
1145 if (state->identity.in_soc) in dib0090_get_slow_adc_val()
1152 struct dib0090_state *state = fe->tuner_priv; in dib0090_gain_control() local
1153 enum frontend_tune_state *tune_state = &state->tune_state; in dib0090_gain_control()
1161 state->agc_freeze = 0; in dib0090_gain_control()
1162 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1165 if (state->current_band == BAND_SBAND) { in dib0090_gain_control()
1166 dib0090_set_rframp(state, rf_ramp_sband); in dib0090_gain_control()
1167 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1171 if (state->current_band == BAND_VHF && !state->identity.p1g) { in dib0090_gain_control()
1172 dib0090_set_rframp(state, rf_ramp_pwm_vhf); in dib0090_gain_control()
1173 dib0090_set_bbramp(state, bb_ramp_pwm_normal); in dib0090_gain_control()
1177 if (state->current_band == BAND_CBAND && !state->identity.p1g) { in dib0090_gain_control()
1178 dib0090_set_rframp(state, rf_ramp_pwm_cband); in dib0090_gain_control()
1179 dib0090_set_bbramp(state, bb_ramp_pwm_normal); in dib0090_gain_control()
1182 …if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g)… in dib0090_gain_control()
1183 dib0090_set_rframp(state, rf_ramp_pwm_cband_7090p); in dib0090_gain_control()
1184 dib0090_set_bbramp(state, bb_ramp_pwm_normal_socs); in dib0090_gain_control()
1186 dib0090_set_rframp(state, rf_ramp_pwm_uhf); in dib0090_gain_control()
1187 dib0090_set_bbramp(state, bb_ramp_pwm_normal); in dib0090_gain_control()
1190 dib0090_write_reg(state, 0x32, 0); in dib0090_gain_control()
1191 dib0090_write_reg(state, 0x39, 0); in dib0090_gain_control()
1193 dib0090_wbd_target(state, state->current_rf); in dib0090_gain_control()
1195 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_control()
1196 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA; in dib0090_gain_control()
1199 } else if (!state->agc_freeze) { in dib0090_gain_control()
1203 wbd_val = dib0090_get_slow_adc_val(state); in dib0090_gain_control()
1211 wbd_val = dib0090_get_slow_adc_val(state); in dib0090_gain_control()
1212 wbd += dib0090_wbd_to_db(state, wbd_val); in dib0090_gain_control()
1215 wbd_error = state->wbd_target - wbd; in dib0090_gain_control()
1218 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) { in dib0090_gain_control()
1221 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; in dib0090_gain_control()
1222 if (state->current_band == BAND_CBAND && ltg2) { in dib0090_gain_control()
1224 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */ in dib0090_gain_control()
1228 state->agc_step = 0; in dib0090_gain_control()
1233 adc = state->config->get_adc_power(fe); in dib0090_gain_control()
1238 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) in dib0090_gain_control()
1242 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && in dib0090_gain_control()
1243 …(state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation ==… in dib0090_gain_control()
1247 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cac… in dib0090_gain_control()
1250 ((state->fe->dtv_property_cache.layer[0].modulation == in dib0090_gain_control()
1252 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1255 ((state->fe->dtv_property_cache.layer[1].segment_count > in dib0090_gain_control()
1258 ((state->fe->dtv_property_cache.layer[1].modulation == in dib0090_gain_control()
1260 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1263 ((state->fe->dtv_property_cache.layer[2].segment_count > in dib0090_gain_control()
1266 ((state->fe->dtv_property_cache.layer[2].modulation == in dib0090_gain_control()
1268 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1276 if (abs(adc_error) < 50 || state->agc_step++ > 5) { in dib0090_gain_control()
1279 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) { in dib0090_gain_control()
1280 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : nar… in dib0090_gain_control()
1281 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1285 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); in dib0090_gain_control()
1286 …dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_gain_control()
1301 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); in dib0090_gain_control()
1306 if (!state->agc_freeze) in dib0090_gain_control()
1307 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); in dib0090_gain_control()
1315 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_current_gain() local
1317 *rf = state->gain[0]; in dib0090_get_current_gain()
1319 *bb = state->gain[1]; in dib0090_get_current_gain()
1321 *rf_gain_limit = state->rf_gain_limit; in dib0090_get_current_gain()
1323 *rflt = (state->rf_lt_def >> 10) & 0x7; in dib0090_get_current_gain()
1330 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_wbd_target() local
1331 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000; in dib0090_get_wbd_target()
1332 s32 current_temp = state->temperature; in dib0090_get_wbd_target()
1334 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_get_wbd_target()
1346 state->wbdmux &= ~(7 << 13); in dib0090_get_wbd_target()
1348 state->wbdmux |= (wbd->wbd_gain << 13); in dib0090_get_wbd_target()
1350 state->wbdmux |= (4 << 13); in dib0090_get_wbd_target()
1352 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_get_wbd_target()
1359 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold); in dib0090_get_wbd_target()
1360 dprintk("wbd-target: %d dB\n", (u32) state->wbd_target); in dib0090_get_wbd_target()
1363 return state->wbd_offset + wbd_tcold; in dib0090_get_wbd_target()
1369 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_wbd_offset() local
1370 return state->wbd_offset; in dib0090_get_wbd_offset()
1376 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_switch() local
1378 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) in dib0090_set_switch()
1387 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_vga() local
1389 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) in dib0090_set_vga()
1397 struct dib0090_state *state = fe->tuner_priv; in dib0090_update_rframp_7090() local
1399 if ((!state->identity.p1g) || (!state->identity.in_soc) in dib0090_update_rframp_7090()
1400 || ((state->identity.version != SOC_7090_P1G_21R1) in dib0090_update_rframp_7090()
1401 && (state->identity.version != SOC_7090_P1G_11R1))) { in dib0090_update_rframp_7090()
1407 state->rf_ramp = rf_ramp_pwm_cband_7090e_sensitivity; in dib0090_update_rframp_7090()
1409 state->rf_ramp = rf_ramp_pwm_cband_7090e_aci; in dib0090_update_rframp_7090()
1479 static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n) in dib0090_set_default_config() argument
1487 dib0090_write_reg(state, r, pgm_read_word(n++)); in dib0090_set_default_config()
1501 static void dib0090_set_EFUSE(struct dib0090_state *state) in dib0090_set_EFUSE() argument
1507 e2 = dib0090_read_reg(state, 0x26); in dib0090_set_EFUSE()
1508 e4 = dib0090_read_reg(state, 0x28); in dib0090_set_EFUSE()
1510 if ((state->identity.version == P1D_E_F) || in dib0090_set_EFUSE()
1511 (state->identity.version == P1G) || (e2 == 0xffff)) { in dib0090_set_EFUSE()
1513 dib0090_write_reg(state, 0x22, 0x10); in dib0090_set_EFUSE()
1514 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; in dib0090_set_EFUSE()
1539 dib0090_write_reg(state, 0x13, (h << 10)); in dib0090_set_EFUSE()
1541 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ in dib0090_set_EFUSE()
1547 struct dib0090_state *state = fe->tuner_priv; in dib0090_reset() local
1549 dib0090_reset_digital(fe, state->config); in dib0090_reset()
1554 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */ in dib0090_reset()
1558 if (!state->identity.in_soc) { in dib0090_reset()
1559 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) in dib0090_reset()
1560 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1562 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1565 dib0090_set_default_config(state, dib0090_defaults); in dib0090_reset()
1567 if (state->identity.in_soc) in dib0090_reset()
1568 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ in dib0090_reset()
1570 if (state->identity.p1g) in dib0090_reset()
1571 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults); in dib0090_reset()
1574 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) in dib0090_reset()
1575 dib0090_set_EFUSE(state); in dib0090_reset()
1578 if (state->config->force_crystal_mode != 0) in dib0090_reset()
1579 dib0090_write_reg(state, 0x14, in dib0090_reset()
1580 state->config->force_crystal_mode & 3); in dib0090_reset()
1581 else if (state->config->io.clock_khz >= 24000) in dib0090_reset()
1582 dib0090_write_reg(state, 0x14, 1); in dib0090_reset()
1584 dib0090_write_reg(state, 0x14, 2); in dib0090_reset()
1585 dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); in dib0090_reset()
1587 …state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibratio… in dib0090_reset()
1594 static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state) in dib0090_get_offset() argument
1601 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_get_offset()
1606 state->adc_diff = dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1609 dib0090_write_reg(state, 0x1f, 0x4); in dib0090_get_offset()
1614 state->adc_diff -= dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1655 static void dib0090_set_trim(struct dib0090_state *state) in dib0090_set_trim() argument
1659 if (state->dc->addr == 0x07) in dib0090_set_trim()
1660 val = &state->bb7; in dib0090_set_trim()
1662 val = &state->bb6; in dib0090_set_trim()
1664 *val &= ~(0x1f << state->dc->offset); in dib0090_set_trim()
1665 *val |= state->step << state->dc->offset; in dib0090_set_trim()
1667 dib0090_write_reg(state, state->dc->addr, *val); in dib0090_set_trim()
1670 static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tun… in dib0090_dc_offset_calibration() argument
1680 state->bb6 = 0; in dib0090_dc_offset_calibration()
1681 state->bb7 = 0x040d; in dib0090_dc_offset_calibration()
1684 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ in dib0090_dc_offset_calibration()
1685 dib0090_write_reg(state, 0x24, reg); in dib0090_dc_offset_calibration()
1687 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_dc_offset_calibration()
1688 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); in dib0090_dc_offset_calibration()
1689 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_dc_offset_calibration()
1691 state->dc = dc_table; in dib0090_dc_offset_calibration()
1693 if (state->identity.p1g) in dib0090_dc_offset_calibration()
1694 state->dc = dc_p1g_table; in dib0090_dc_offset_calibration()
1699 (state->dc->i == 1) ? "I" : "Q"); in dib0090_dc_offset_calibration()
1700 dib0090_write_reg(state, 0x01, state->dc->bb1); in dib0090_dc_offset_calibration()
1701 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); in dib0090_dc_offset_calibration()
1703 state->step = 0; in dib0090_dc_offset_calibration()
1704 state->min_adc_diff = 1023; in dib0090_dc_offset_calibration()
1710 dib0090_set_trim(state); in dib0090_dc_offset_calibration()
1717 ret = dib0090_get_offset(state, tune_state); in dib0090_dc_offset_calibration()
1721 dprintk("adc_diff = %d, current step= %d\n", (u32) state->adc_diff, state->step); in dib0090_dc_offset_calibration()
1722 if (state->step == 0 && state->adc_diff < 0) { in dib0090_dc_offset_calibration()
1723 state->min_adc_diff = -1023; in dib0090_dc_offset_calibration()
1727 …adc_diff = %d, min_adc_diff = %d current_step = %d\n", state->adc_diff, state->min_adc_diff, state… in dib0090_dc_offset_calibration()
1730 if (state->step == 0) { in dib0090_dc_offset_calibration()
1731 if (state->dc->pga && state->adc_diff < 0) in dib0090_dc_offset_calibration()
1732 state->step = 0x10; in dib0090_dc_offset_calibration()
1733 if (state->dc->pga == 0 && state->adc_diff > 0) in dib0090_dc_offset_calibration()
1734 state->step = 0x10; in dib0090_dc_offset_calibration()
1738 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) { in dib0090_dc_offset_calibration()
1740 state->step++; in dib0090_dc_offset_calibration()
1741 state->min_adc_diff = state->adc_diff; in dib0090_dc_offset_calibration()
1745 if (abs(state->adc_diff) > abs(state->min_adc_diff)) { in dib0090_dc_offset_calibration()
1746 …dc_diff N = %d > adc_diff step N-1 = %d, Come back one step\n", state->adc_diff, state->min_adc_d… in dib0090_dc_offset_calibration()
1747 state->step--; in dib0090_dc_offset_calibration()
1750 dib0090_set_trim(state); in dib0090_dc_offset_calibration()
1752 state->dc->addr, state->adc_diff, state->step); in dib0090_dc_offset_calibration()
1754 state->dc++; in dib0090_dc_offset_calibration()
1755 if (state->dc->addr == 0) /* done */ in dib0090_dc_offset_calibration()
1764 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); in dib0090_dc_offset_calibration()
1765 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_dc_offset_calibration()
1767 state->calibrate &= ~DC_CAL; in dib0090_dc_offset_calibration()
1776 static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_stat… in dib0090_wbd_calibration() argument
1779 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_wbd_calibration()
1783 while (state->current_rf / 1000 > wbd->max_freq) in dib0090_wbd_calibration()
1790 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) in dib0090_wbd_calibration()
1795 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */ in dib0090_wbd_calibration()
1797 state->calibrate &= ~WBD_CAL; in dib0090_wbd_calibration()
1801 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); in dib0090_wbd_calibration()
1803 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); in dib0090_wbd_calibration()
1805 state->wbd_calibration_gain = wbd_gain; in dib0090_wbd_calibration()
1809 state->wbd_offset = dib0090_get_slow_adc_val(state); in dib0090_wbd_calibration()
1810 dprintk("WBD calibration offset = %d\n", state->wbd_offset); in dib0090_wbd_calibration()
1812 state->calibrate &= ~WBD_CAL; in dib0090_wbd_calibration()
1821 static void dib0090_set_bandwidth(struct dib0090_state *state) in dib0090_set_bandwidth() argument
1825 if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000) in dib0090_set_bandwidth()
1827 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000) in dib0090_set_bandwidth()
1829 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000) in dib0090_set_bandwidth()
1834 state->bb_1_def &= 0x3fff; in dib0090_set_bandwidth()
1835 state->bb_1_def |= tmp; in dib0090_set_bandwidth()
1837 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ in dib0090_set_bandwidth()
1839 …dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte… in dib0090_set_bandwidth()
1840 …dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_set_bandwidth()
1841 if (state->identity.in_soc) { in dib0090_set_bandwidth()
1842 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n… in dib0090_set_bandwidth()
1844 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ in dib0090_set_bandwidth()
1845 …dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias… in dib0090_set_bandwidth()
2043 struct dib0090_state *state = fe->tuner_priv; in dib0090_update_tuning_table_7090() local
2052 if ((!state->identity.p1g) || (!state->identity.in_soc) in dib0090_update_tuning_table_7090()
2053 || ((state->identity.version != SOC_7090_P1G_21R1) in dib0090_update_tuning_table_7090()
2054 && (state->identity.version != SOC_7090_P1G_11R1))) { in dib0090_update_tuning_table_7090()
2064 while (state->rf_request > tune->max_freq) in dib0090_update_tuning_table_7090()
2067 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) in dib0090_update_tuning_table_7090()
2069 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) in dib0090_update_tuning_table_7090()
2075 static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state) in dib0090_captrim_search() argument
2085 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_captrim_search()
2091 dib0090_write_reg(state, 0x10, 0x2B1); in dib0090_captrim_search()
2092 dib0090_write_reg(state, 0x1e, 0x0032); in dib0090_captrim_search()
2094 if (!state->tuner_is_tuned) { in dib0090_captrim_search()
2096 if (!state->identity.p1g || force_soft_search) in dib0090_captrim_search()
2097 state->step = state->captrim = state->fcaptrim = 64; in dib0090_captrim_search()
2099 state->current_rf = state->rf_request; in dib0090_captrim_search()
2101 if (!state->identity.p1g || force_soft_search) { in dib0090_captrim_search()
2103 state->step = 4; in dib0090_captrim_search()
2104 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; in dib0090_captrim_search()
2107 state->adc_diff = 3000; in dib0090_captrim_search()
2111 if (state->identity.p1g && !force_soft_search) { in dib0090_captrim_search()
2114 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); in dib0090_captrim_search()
2115 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2118 state->step /= 2; in dib0090_captrim_search()
2119 dib0090_write_reg(state, 0x18, lo4 | state->captrim); in dib0090_captrim_search()
2121 if (state->identity.in_soc) in dib0090_captrim_search()
2127 if (state->identity.p1g && !force_soft_search) { in dib0090_captrim_search()
2128 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); in dib0090_captrim_search()
2129 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2131 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; in dib0090_captrim_search()
2132 dprintk("***Final Captrim= 0x%x\n", state->fcaptrim); in dib0090_captrim_search()
2137 adc = dib0090_get_slow_adc_val(state); in dib0090_captrim_search()
2138 …dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV\n", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32… in dib0090_captrim_search()
2140 …if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug… in dib0090_captrim_search()
2153 if (adc < state->adc_diff) { in dib0090_captrim_search()
2154 …printk("CAPTRIM=%d is closer to target (%d/%d)\n", (u32) state->captrim, (u32) adc, (u32) state->a… in dib0090_captrim_search()
2155 state->adc_diff = adc; in dib0090_captrim_search()
2156 state->fcaptrim = state->captrim; in dib0090_captrim_search()
2159 state->captrim += step_sign * state->step; in dib0090_captrim_search()
2160 if (state->step >= 1) in dib0090_captrim_search()
2169 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); in dib0090_captrim_search()
2174 state->calibrate &= ~CAPTRIM_CAL; in dib0090_captrim_search()
2181 static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_stat… in dib0090_get_temperature() argument
2188 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_get_temperature()
2189 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); in dib0090_get_temperature()
2191 state->bias = dib0090_read_reg(state, 0x13); in dib0090_get_temperature()
2192 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); in dib0090_get_temperature()
2199 state->adc_diff = dib0090_get_slow_adc_val(state); in dib0090_get_temperature()
2200 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); in dib0090_get_temperature()
2205 val = dib0090_get_slow_adc_val(state); in dib0090_get_temperature()
2206 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; in dib0090_get_temperature()
2208 dprintk("temperature: %d C\n", state->temperature - 30); in dib0090_get_temperature()
2214 dib0090_write_reg(state, 0x13, state->bias); in dib0090_get_temperature()
2215 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ in dib0090_get_temperature()
2218 state->calibrate &= ~TEMP_CAL; in dib0090_get_temperature()
2219 if (state->config->analog_output == 0) in dib0090_get_temperature()
2220 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_get_temperature()
2234 struct dib0090_state *state = fe->tuner_priv; in dib0090_tune() local
2235 const struct dib0090_tuning *tune = state->current_tune_table_index; in dib0090_tune()
2236 const struct dib0090_pll *pll = state->current_pll_table_index; in dib0090_tune()
2237 enum frontend_tune_state *tune_state = &state->tune_state; in dib0090_tune()
2252 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL)) in dib0090_tune()
2253 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_tune()
2256 if (state->config->analog_output == 0) in dib0090_tune()
2257 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_tune()
2260 if (state->calibrate & DC_CAL) in dib0090_tune()
2261 return dib0090_dc_offset_calibration(state, tune_state); in dib0090_tune()
2262 else if (state->calibrate & WBD_CAL) { in dib0090_tune()
2263 if (state->current_rf == 0) in dib0090_tune()
2264 state->current_rf = state->fe->dtv_property_cache.frequency / 1000; in dib0090_tune()
2265 return dib0090_wbd_calibration(state, tune_state); in dib0090_tune()
2266 } else if (state->calibrate & TEMP_CAL) in dib0090_tune()
2267 return dib0090_get_temperature(state, tune_state); in dib0090_tune()
2268 else if (state->calibrate & CAPTRIM_CAL) in dib0090_tune()
2269 return dib0090_captrim_search(state, tune_state); in dib0090_tune()
2273 if (state->config->use_pwm_agc && state->identity.in_soc) { in dib0090_tune()
2274 tmp = dib0090_read_reg(state, 0x39); in dib0090_tune()
2276 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); in dib0090_tune()
2279 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000); in dib0090_tune()
2280 state->rf_request = in dib0090_tune()
2281 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band == in dib0090_tune()
2282 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config-> in dib0090_tune()
2286 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.i… in dib0090_tune()
2287 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) { in dib0090_tune()
2288 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if; in dib0090_tune()
2294 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz)) in dib0090_tune()
2295 && (state->rf_request < (LUT_offset->RF_freq + margin_khz))) in dib0090_tune()
2296 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) { in dib0090_tune()
2297 state->rf_request += LUT_offset->offset_khz; in dib0090_tune()
2306 state->rf_request += 400; in dib0090_tune()
2308 …if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_… in dib0090_tune()
2309 state->tuner_is_tuned = 0; in dib0090_tune()
2310 state->current_rf = 0; in dib0090_tune()
2311 state->current_standard = 0; in dib0090_tune()
2314 if (state->identity.p1g) in dib0090_tune()
2317 tmp = (state->identity.version >> 5) & 0x7; in dib0090_tune()
2319 if (state->identity.in_soc) { in dib0090_tune()
2320 if (state->config->force_cband_input) { /* Use the CBAND input for all band */ in dib0090_tune()
2321 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN… in dib0090_tune()
2322 || state->current_band & BAND_UHF) { in dib0090_tune()
2323 state->current_band = BAND_CBAND; in dib0090_tune()
2324 if (state->config->is_dib7090e) in dib0090_tune()
2330 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN… in dib0090_tune()
2331 state->current_band = BAND_CBAND; in dib0090_tune()
2332 if (state->config->is_dib7090e) in dib0090_tune()
2341 …if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == … in dib0090_tune()
2342 state->current_band = BAND_CBAND; /* Force CBAND */ in dib0090_tune()
2345 if (state->identity.p1g) in dib0090_tune()
2351 if (state->identity.p1g) in dib0090_tune()
2355 while (state->rf_request > tune->max_freq) in dib0090_tune()
2357 while (state->rf_request > pll->max_freq) in dib0090_tune()
2360 state->current_tune_table_index = tune; in dib0090_tune()
2361 state->current_pll_table_index = pll; in dib0090_tune()
2363 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); in dib0090_tune()
2365 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; in dib0090_tune()
2367 FREF = state->config->io.clock_khz; in dib0090_tune()
2368 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2369 FREF /= state->config->fref_clock_ratio; in dib0090_tune()
2384 state->rest = Rest; in dib0090_tune()
2398 else if (state->config->analog_output) in dib0090_tune()
2404 if (state->identity.p1g) { /* Bias is done automatically in P1G */ in dib0090_tune()
2405 if (state->identity.in_soc) { in dib0090_tune()
2406 if (state->identity.version == SOC_8090_P1G_11R1) in dib0090_tune()
2416 if (!state->config->io.pll_int_loop_filt) { in dib0090_tune()
2417 if (state->identity.in_soc) in dib0090_tune()
2419 else if (state->identity.p1g || (Rest == 0)) in dib0090_tune()
2424 lo6 = (state->config->io.pll_int_loop_filt << 3); in dib0090_tune()
2432 dib0090_write_reg(state, 0x15, (u16) FBDiv); in dib0090_tune()
2433 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2434 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); in dib0090_tune()
2436 dib0090_write_reg(state, 0x16, (Den << 8) | 1); in dib0090_tune()
2437 dib0090_write_reg(state, 0x17, (u16) Rest); in dib0090_tune()
2438 dib0090_write_reg(state, 0x19, lo5); in dib0090_tune()
2439 dib0090_write_reg(state, 0x1c, lo6); in dib0090_tune()
2442 if (state->config->analog_output) in dib0090_tune()
2445 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); in dib0090_tune()
2449 state->current_rf = state->rf_request; in dib0090_tune()
2450 state->current_standard = state->fe->dtv_property_cache.delivery_system; in dib0090_tune()
2453 state->calibrate = CAPTRIM_CAL; /* captrim search now */ in dib0090_tune()
2457 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_tune()
2459 while (state->current_rf / 1000 > wbd->max_freq) in dib0090_tune()
2462 dib0090_write_reg(state, 0x1e, 0x07ff); in dib0090_tune()
2463 dprintk("Final Captrim: %d\n", (u32) state->fcaptrim); in dib0090_tune()
2466 …kHz: %d ((%d*%d) << 1))\n", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) … in dib0090_tune()
2467 dprintk("REFDIV: %d, FREF: %d\n", (u32) 1, (u32) state->config->io.clock_khz); in dib0090_tune()
2468 …printk("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state,… in dib0090_tune()
2469 …k("Num: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state… in dib0090_tune()
2470 (u32) dib0090_read_reg(state, 0x1c) & 0x3); in dib0090_tune()
2479 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1)); in dib0090_tune()
2480 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_tune()
2482 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) { in dib0090_tune()
2484 dib0090_write_reg(state, 0x09, tune->lna_bias); in dib0090_tune()
2485 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); in dib0090_tune()
2487 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); in dib0090_tune()
2489 dib0090_write_reg(state, 0x0c, tune->v2i); in dib0090_tune()
2490 dib0090_write_reg(state, 0x0d, tune->mix); in dib0090_tune()
2491 dib0090_write_reg(state, 0x0e, tune->load); in dib0090_tune()
2496 state->rf_lt_def = 0x7c00; in dib0090_tune()
2498 dib0090_set_bandwidth(state); in dib0090_tune()
2499 state->tuner_is_tuned = 1; in dib0090_tune()
2501 state->calibrate |= WBD_CAL; in dib0090_tune()
2502 state->calibrate |= TEMP_CAL; in dib0090_tune()
2517 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_tune_state() local
2519 return state->tune_state; in dib0090_get_tune_state()
2526 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_tune_state() local
2528 state->tune_state = tune_state; in dib0090_set_tune_state()
2536 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_frequency() local
2538 *frequency = 1000 * state->current_rf; in dib0090_get_frequency()
2544 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_params() local
2547 state->tune_state = CT_TUNER_START; in dib0090_set_params()
2564 } while (state->tune_state != CT_TUNER_STOP); in dib0090_set_params()