Lines Matching refs:GENMASK_ULL
128 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
158 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
178 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
199 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
200 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
204 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
210 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
213 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
214 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
216 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
225 #define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2)
226 #define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4)
227 #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6)
231 #define STRTAB_STE_1_EATS GENMASK_ULL(29, 28)
236 #define STRTAB_STE_1_STRW GENMASK_ULL(31, 30)
240 #define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44)
243 #define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0)
244 #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
245 #define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0)
246 #define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6)
247 #define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8)
248 #define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10)
249 #define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12)
250 #define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14)
251 #define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16)
257 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
271 #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
274 #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
275 #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
276 #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
277 #define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
278 #define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12)
285 #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
293 #define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
295 #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
323 #define CMDQ_0_OP GENMASK_ULL(7, 0)
326 #define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32)
327 #define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0)
328 #define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
330 #define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12)
331 #define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)
333 #define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)
335 #define CMDQ_TLBI_0_NUM GENMASK_ULL(16, 12)
337 #define CMDQ_TLBI_0_SCALE GENMASK_ULL(24, 20)
338 #define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)
339 #define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)
341 #define CMDQ_TLBI_1_TTL GENMASK_ULL(9, 8)
342 #define CMDQ_TLBI_1_TG GENMASK_ULL(11, 10)
343 #define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
344 #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
346 #define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12)
347 #define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)
349 #define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0)
350 #define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)
352 #define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12)
353 #define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)
354 #define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0)
355 #define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12)
360 #define CMDQ_RESUME_0_RESP GENMASK_ULL(13, 12)
361 #define CMDQ_RESUME_0_SID GENMASK_ULL(63, 32)
362 #define CMDQ_RESUME_1_STAG GENMASK_ULL(15, 0)
364 #define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12)
368 #define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22)
369 #define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24)
370 #define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32)
371 #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
378 #define EVTQ_0_ID GENMASK_ULL(7, 0)
386 #define EVTQ_0_SSID GENMASK_ULL(31, 12)
387 #define EVTQ_0_SID GENMASK_ULL(63, 32)
388 #define EVTQ_1_STAG GENMASK_ULL(15, 0)
394 #define EVTQ_1_CLASS GENMASK_ULL(41, 40)
396 #define EVTQ_2_ADDR GENMASK_ULL(63, 0)
397 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
404 #define PRIQ_0_SID GENMASK_ULL(31, 0)
405 #define PRIQ_0_SSID GENMASK_ULL(51, 32)
413 #define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0)
414 #define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)