Lines Matching refs:DEFINE_QBCM

159 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
160 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
161 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
162 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
163 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_u…
164 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
165 DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
166 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
167 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
168 DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
169 DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
170 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
171 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
172 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
173 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
174 DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
175 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
176 DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2…
177 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
178 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
179 DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
180 DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
181 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
182 DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
183 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
184 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
185 DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
186 DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
187 DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);