Lines Matching refs:GENMASK_ULL

372 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
373 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
374 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
375 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
376 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
377 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
378 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
379 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
380 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
383 #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
386 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
391 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
392 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
393 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(5, 0)
395 #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(53, 52)
399 #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
400 #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
401 #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
402 #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
403 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
404 #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)
405 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
406 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
407 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
412 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
413 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
414 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
416 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
417 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
418 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
419 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
420 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
421 #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
424 #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
425 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
426 #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
427 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
428 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
429 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
430 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
431 #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
433 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
434 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
439 #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
440 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
442 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
444 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
445 #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
446 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
448 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
449 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
450 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
451 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
454 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
459 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
461 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
462 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
463 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
473 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
474 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
478 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
479 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
480 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
481 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
482 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
483 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
485 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
490 #define IRDMACQ_OP GENMASK_ULL(61, 56)
492 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
497 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
499 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
501 #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
502 #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
503 #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
504 #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
505 #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
508 #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
509 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
510 #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
511 #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
512 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
515 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
516 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
517 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
518 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
519 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
520 #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
522 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
523 #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
525 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
526 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
528 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
530 #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)
537 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
538 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
553 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
559 #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
562 #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
566 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
567 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
570 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
572 #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
578 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
582 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
583 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
584 #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
586 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
592 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
593 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
600 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
602 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
604 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
607 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
608 #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
609 #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
610 #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
611 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
612 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
613 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
614 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
615 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
619 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
620 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
621 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
623 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
629 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
630 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
631 #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
637 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
638 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
643 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
646 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
647 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
648 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
649 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
654 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
655 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
658 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
660 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
663 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
664 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
665 #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
666 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
667 #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
668 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
669 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
670 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
675 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
677 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
678 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
679 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
680 #define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
687 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
688 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
690 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
691 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
701 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
708 #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
710 #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
714 #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
716 #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
722 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
724 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
725 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
729 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
730 #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
731 #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
734 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
735 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
736 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
737 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
738 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
739 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
740 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
741 #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
742 #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
743 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
744 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
745 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
750 #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
751 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
752 #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
753 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
754 #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
755 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
756 #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
757 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
758 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
759 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
760 #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
761 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
762 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
763 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
764 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
765 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
766 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
767 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
768 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
769 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
770 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
771 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
772 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
773 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
774 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
775 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
776 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
777 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
778 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
779 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
780 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
781 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
782 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
783 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
784 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
785 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
786 #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
787 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
788 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
789 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
790 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
791 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
792 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
793 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
795 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
808 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
809 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
810 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
816 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
817 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
820 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
821 #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
822 #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
823 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
824 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
825 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
826 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
827 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
828 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
829 #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
830 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
831 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
832 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
834 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
836 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
843 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
849 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
850 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
851 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
852 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
853 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
854 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
855 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
856 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
860 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
864 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
865 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
869 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
874 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
875 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
879 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
881 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
882 #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
884 #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
885 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
886 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
887 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
888 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
889 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
903 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
904 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
905 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
906 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
907 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
908 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
909 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
910 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
911 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
912 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
913 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
914 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
915 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)