Lines Matching refs:ICMCR
35 #define ICMCR 0x04 /* master ctrl */ macro
169 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); in rcar_i2c_get_scl()
182 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); in rcar_i2c_set_scl()
194 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); in rcar_i2c_set_sda()
201 return !(rcar_i2c_read(priv, ICMCR) & FSDA); in rcar_i2c_get_bus_free()
216 rcar_i2c_write(priv, ICMCR, MDBS); in rcar_i2c_init()
231 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, in rcar_i2c_bus_barrier()
357 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); in rcar_i2c_prepare_msg()
523 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); in rcar_i2c_irq_send()
574 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); in rcar_i2c_irq_recv()
576 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); in rcar_i2c_irq_recv()
709 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); in rcar_i2c_gen2_irq()
734 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); in rcar_i2c_gen3_irq()