Lines Matching refs:off_mask
51 u32 off_mask; in etm4_cfg_map_reg_offset() local
86 off_mask = (offset & GENMASK(11, 5)); in etm4_cfg_map_reg_offset()
88 CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); in etm4_cfg_map_reg_offset()
89 CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); in etm4_cfg_map_reg_offset()
90 CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); in etm4_cfg_map_reg_offset()
95 off_mask = (offset & GENMASK(11, 6)); in etm4_cfg_map_reg_offset()
97 CHECKREGIDX(TRCCIDCVRn(0), ctxid_pid, idx, off_mask); in etm4_cfg_map_reg_offset()
98 CHECKREGIDX(TRCVMIDCVRn(0), vmid_val, idx, off_mask); in etm4_cfg_map_reg_offset()
112 off_mask = offset & GENMASK(11, 7); in etm4_cfg_map_reg_offset()
114 CHECKREGIDX(TRCACVRn(0), addr_val, idx, off_mask); in etm4_cfg_map_reg_offset()
115 CHECKREGIDX(TRCACATRn(0), addr_acc, idx, off_mask); in etm4_cfg_map_reg_offset()
121 off_mask = offset & GENMASK(11, 4); in etm4_cfg_map_reg_offset()
123 CHECKREGIDX(TRCCNTRLDVRn(0), cntrldvr, idx, off_mask); in etm4_cfg_map_reg_offset()
124 CHECKREGIDX(TRCCNTCTLRn(0), cntr_ctrl, idx, off_mask); in etm4_cfg_map_reg_offset()
125 CHECKREGIDX(TRCCNTVRn(0), cntr_val, idx, off_mask); in etm4_cfg_map_reg_offset()